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1 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group package type : 64p6u-a/64p6q-a fig. 1 pin configuration of 38k2 group pin configuration (top view) description the 38k2 group is the 8-bit microcomputer based on the 740 fam- ily core technology. the 38k2 group has the usb function, an 8-bit bus interface, a serial i/o, three 8-bit timers, and an 8-channel 10-bit a-d con- verter, which are available for the pc peripheral i/o device. the various microcomputers in the 38k2 group include variations of internal memory size and packaging. for details, refer to the section on part numbering. features basic machine-language instructions ....................................... 71 the minimum instruction execution time .......................... 0.25 ? (at 8 mhz system clock ? ) system clock ? : reference frequency to internal circuit except usb function memory size rom ................................................................ 16 k to 32 k bytes ram ............................................................... 1024 to 2048 bytes programmable input/output ports ............................................. 44 software pull-up resistors interrupts .................................................. 16 sources, 16 vectors usb function (usb version 1.1 specification) ........... 4 endpoints usb hub function (usb version 1.1 specification) . 2 down ports external bus interface ....................................... 8-bit ? 1 channel timers ............................................................................. 8-bit ? 3 watchdog timer ............................................................. 16-bit ? 1 serial i/o ...................... 8-bit ? 1 (uart or clock-synchronized) a-d converter ................................................ 10-bit ? 8 channels (8-bit reading available) led direct drive port ................................................................... 4 clock generating circuit (connect to external ceramic resonator or quartz-crystal oscillator) power source voltage system clock/internal clock division mode at 12 mhz/through mode ( = 12 mhz) ...................................... ......................................................... 4.50 to 5.25 v (under planning) at 12 mhz/2-divide mode( = 6 mhz) .......................................... ............................................. 4.00 to 5.25 v (under development) at 8 mhz/through mode ( = 8 mhz) ................... 4.00 to 5.25 v at 6 mhz/through mode ( = 6 mhz) ................... 4.00 to 5.25 v at 6 mhz/through mode ( = 6 mhz) .......................................... ............................................. 3.00 to 4.00 v (under development) remarks : the mode under development will be available from aug./2002. power dissipation at 5 v power source voltage .................................. 125 mw (typ.) (at 8 mhz system clock, in through mode) at 3.3 v power source voltage ................................ 45 mw (typ.) (at 6 mhz system clock, in through mode) operating temperature range .................................... ?0 to 85? packages fp ........................................ 64p6u-a (64-pin 14 ? 14 mm lqfp) hp ........................................ 64p6q-a (64-pin 10 ? 10 mm lqfp) notes 1. the specifications of this product are subject to change be- cause it is under development. inquire the use of mitsubishi electric corporation. 2. the flash memory version cannot be used for application em- bedded in the mcu card. 3 2 3 1 3 0 2 9 2 8 2 6 2 5 2 4 2 3 2 2 2 1 20 1 9 1 8 17 4 9 5 0 5 1 5 2 5 3 5 4 5 5 56 5 7 5 8 59 6 0 6 1 6 2 6 3 2 7 64 4 8 4 7 4 6 4 5 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 4 4 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 tron d2+ d2- d1+ d1- d0- d0+ usbv ref dv cc pv cc p 0 3 p 0 2 p 0 1 p 0 0 p 5 7 p 5 6 p 5 5 p 5 4 p 5 3 p 5 2 / i n t 1 p 5 1 / c n t r 0 p 5 0 / i n t 0 pv ss p 1 0 / d q 0 / a n 0 p 0 6 p 0 7 p 4 0 / e x d r e q / r x d p 1 1 / d q 1 / a n 1 p 1 2 / d q 2 / a n 2 p 1 3 / d q 3 / a n 3 p 1 4 / d q 4 / a n 4 p 1 5 / d q 5 / a n 5 p 1 6 / d q 6 / a n 6 p 1 7 / d q 7 / a n 7 p 6 0 ( l e d 0 ) p6 1 (led 1 ) p6 2 (led 2 ) p6 3 (led 3 ) p 4 1 / e x d a c k / t x d p4 2 /e x tc/s clk p4 3 /e x a1/s rdy p 3 0 p3 1 p 3 2 p 3 3 / e x i n t p 3 4 / e x c s p3 5 /e x wr p 3 6 / e x r d p 3 7 / e x a 0 M38K27M4-XXXFP/hp m38k29f8fp/h p p2 4 p 0 4 p 2 7 p 2 6 c n v s s v c c e v r e f v s s x o u t v c c c n v s s 2 x i n r e s e t p2 5 p 0 5
2 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group functional block diagram (package : 64p6u-a/64p6q-a) fig. 2 functional block diagram c n t r 0 v s s r e s e t v c c x i n w a t c h d o g t i m e r t i m e r x ( 8 ) t i m e r 1 ( 8 ) t i m e r 2 ( 8 ) x o u t c l o c k g e n e r a t i n g c i r c u i t r a m d a t a b u s c p u r a m i / f r o m c n v s s c n v s s 2 p v c c p v s s p 5 ( 8 ) i n t 1 i n t 0 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 p 6 ( 4 ) 1 6 1 7 1 8 1 9 p 4 ( 4 ) s i / o e x t b u s ( 8 ) p 3 ( 8 ) 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 d 0 + u s b d 0 - t r o n u s b v r e f d v c c 2 2 2 3 2 4 2 6 2 5 p 0 ( 8 ) 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 v r e f p 1 ( 8 ) 1 0 - b i t a - d c o n v e r t e r ( 8 ) 1 0 6 3 6 4 1 2 3 4 5 6 2 0 2 1 1 2 1 3 1 1 1 4 8 7 1 5 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 v c c e 9 p 2 ( 4 ) u s b h u b d 1 - d 1 + d 2 - d 2 +
3 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group pin description table 1. pin description function apply voltage of 3.0 v 5.25 v to v cc , and 0 v to v ss . power source pin for ports p1, p3, p4 and analog circuit. connect this pin to v cc . this pin controls the operation mode of the chip. connect this pin to v ss . in the flash memory mode, this pin becoems v pp power source input pin. this pin controls the operation mode of the chip. connect this pin to v ss . reference voltage input pin for a-d converter. power source pin for analog circuit. connect the dv cc and pv cc pins to v cc , and the pv ss pin to v ss . reset input pin for active l input and output pins for the main clock generating circuit. connect a ceramic resonator or a quartz-crystal oscillator between the x in and x out pins to set the oscillation frequency. if an external clock is used, connect the clock source to the x in pin and leave the x out pin open. power source pin for usb port circuit. in vcc = 4.00 to 5.25 v use the built-in usb reference voltage circuit. in vcc = 3.00 to 4.00 v apply 3.3 v power supply from the external because use of the built-in usb reference voltage circuit is prohibited in this voltage range. in vcc = 3.00 to 3.60 v connect this pin to v cc . output pin to pull-up d0+ by 1.5 k ? external resistor. usb upstream i/o port usb input level usb output level output structure usb downstream i/o port usb input level usb output level output structure 8-bit i/o port i/o direction register allows each pin to be individually programmed as either input or output. cmos compatible input level cmos 3-state output structure pull-up control is enabled. 8-bit i/o port i/o direction register allows each pin to be individually programmed as either input or output. cmos compatible input level cmos 3-state output structure 4-bit i/o port i/o direction register allows each pin to be individually programmed as either input or output. cmos compatible input level cmos 3-state output structure 8-bit i/o port i/o direction register allows each pin to be individually programmed as either input or output. cmos compatible input level cmos 3-state output structure 4-bit i/o port i/o direction register allows each pin to be individually programmed as either input or output. cmos compatible input level cmos 3-state output structure 8-bit i/o port i/o direction register allows each pin to be individually programmed as either input or output. cmos compatible input level cmos 3-state output structure 4-bit i/o port; i/o direction register allows each pin to be individually programmed as either input or output.; cmos compatible input level cmos 3-state output structure; output large current for led drive is enabled. key input pins (key-on wake up interrupt) a-d converter input pins external bus interface function pins external bus interface function pins serial i/o function pins external bus interface function pins interrupt input pin timer x funciton pin interrupt input pin pin v cc , v ss v cc e cnv ss cnv ss 2 v ref dv cc pv cc , pv ss reset x in x out usbv ref tron d0+, d0- d1+, d1-, d2+, d2- p0 0 p0 7 p1 0 /dq 0 /an 0 p1 7 /dq 7 /an 7 p2 4 p2 7 p3 0 p3 2 p3 3 /exint p3 4 /excs p3 5 /exwr p3 6 /exrd p3 7 /exa0 p4 0 /exdreq/rxd p4 1 /exdack/txd p4 2 /extc/s clk p4 3 /exa1/s rdy p5 0 /int 0 p5 1 /cntr 0 p5 2 /int 1 p5 3 p5 7 p6 0 p6 3 name power source analog power source cnv ss cnv ss 2 analog reference voltage input analog power source reset input clock input clock output usb reference power source usb reference voltage output usb upstream i/o usb down- stream i/o i/o port p0 i/o port p1 i/o port p2 i/o port p3 i/o port p4 i/o port p5 i/o port p6 function except a port function
4 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group part numbering fig. 3 part numbering m 3 8 k 2 7 m 4 - x x x f p p r o d u c t r o m / p r o m s i z e 1 : 4 0 9 6 b y t e s 2 : 8 1 9 2 b y t e s 3 : 1 2 2 8 8 b y t e s 4 : 1 6 3 8 4 b y t e s 5 : 2 0 4 8 0 b y t e s 6 : 2 4 5 7 6 b y t e s 7 : 2 8 6 7 2 b y t e s 8 : 3 2 7 6 8 b y t e s t h e f i r s t 1 2 8 b y t e s a n d t h e l a s t 2 b y t e s o f r o m a r e r e s e r v e d a r e a s ; t h e y c a n n o t b e u s e d a s a u s e r s r o m a r e a . h o w e v e r , t h e y c a n b e p r o g r a m m e d o r e r a s e d i n t h e f l a s h m e m o r y v e r s i o n , s o t h a t u s e r s c a n u s e t h e m . m e m o r y t y p e m : m a s k r o m v e r s i o n f : f l a s h m e m o r y v e r s i o n ram size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes 8 : 1536 bytes 9 : 2048 bytes rom number omitted in the flash memory version. : standard omitted in the flash memory version. p a c k a g e t y p e f p : 6 4 p 6 u - a p a c k a g e h p : 6 4 p 6 q - a p a c k a g e 9 : 36864 bytes a : 40960 bytes b : 45056 bytes c : 49152 bytes d : 53248 bytes e : 57344 bytes f : 61440 bytes
5 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group group expansion mitsubishi plans to expand the 38k2 group as follows. memory type support for mask rom and flash memory versions. memory size flash memory size .......................................................... 32 kbytes mask rom size ............................................................... 16 kbytes ram size .......................................................... 1024 to 2048 bytes packages 64p6u-a .................................. 0.8 mm-pitch plastic molded lqfp 64p6q-a .................................. 0.5 mm-pitch plastic molded lqfp 100d0m ........................... 0.65 mm-pitch metal seal piggy back memory expansion plan fig. 4 memory expansion plan currently products are listed below. table 2. list of products as of february 2002 remarks package 64p6u-a 64p6q-a 64p6u-a 64p6q-a 100d0m product M38K27M4-XXXFP m38k27m4-xxxhp m38k29f8fp m38k29f8hp m38k29rfs ram size (bytes) 1024 2048 2048 16384 (16254) rom size (bytes) rom size for user in ( ) 32768 (32638) mask rom version flash memory version emulator mcu (for program evaluation) 2 5 65 1 21 , 0 2 42 , 0 4 8 8 k 1 6 k 3 2 k 6 0 k r o m s i z e ( b y t e s ) r a m s i z e ( b y t e s ) m 3 8 k 2 7 m 4 m 3 8 k 2 9 f 8 : u n d e r d e v e l o p m e n t p r o d u c t s u n d e r d e v e l o p m e n t o r p l a n n i n g : t h e d e v e l o p m e n t s c h e d u l e a n d s p e c i f i c a t i o n m a y b e r e v i s e d w i t h o u t n o t i c e . t h e d e v e l o p m e n t o f p l a n n i n g p r o d u c t s m a y b e s t o p p e d .
6 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group functional description central processing unit (cpu) the 38k2 group uses the standard 740 family instruction set. re- fer to the table of 740 family addressing modes and machine instructions or the 740 family software manual for details on the instruction set. machine-resident 740 family instructions are as follows: the fst and slw instruction cannot be used. the stp, wit, mul, and div instruction can be used. the cpu has the 6 registers. the register structure is shown in figure 5. [accumulator (a)] the accumulator is an 8-bit register. data operations such as data transfer, etc., are executed mainly through the accumulator. [index register x (x)] the index register x is an 8-bit register. in the index addressing modes, the value of the operand is added to the contents of register x and specifies the real address. [index register y (y)] the index register y is an 8-bit register. in partial instruction, the value of the operand is added to the contents of register y and specifies the real address. [stack pointer (s)] the stack pointer is an 8-bit register used during subroutine calls and interrupts. this register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. the low-order 8 bits of the stack address are determined by the contents of the stack pointer. the high-order 8 bits of the stack address are determined by the stack page selection bit. if the stack page selection bit is 0 , the high-order 8 bits becomes 00 16 . if the stack page selection bit is 1 , the high-order 8 bits becomes 01 16 . figure 6 shows the store and the return movement into the stack. if there are registers other than those described in figure 5, the users need to store them with the program. [program counter (pc)] the program counter is a 16-bit counter consisting of two 8-bit registers pc h and pc l . it is used to indicate the address of the next instruction to be executed. fig. 5 740 family cpu register structure a accumulator b7 b7 b7 b7 b0 b7 b15 b0 b7 b0 b0 b0 b0 x index register x y index register y s stack pointer pc l program counter pc h n v t b d i z c processor status register (ps) carry flag zero flag interrupt disable flag decimal mode flag break flag index x mode flag overflow flag negative flag
7 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group table 3 push and pop instructions of accumulator or processor status register accumulator processor status register push instruction to stack pha php pop instruction from stack pla plp fig. 6 register push and pop at interrupt generation and subroutine call n o t e : c o n d i t i o n f o r a c c e p t a n c e o f a n i n t e r r u p t i n t e r r u p t e n a b l e f l a g i s 1 e x e c u t e j s r o n - g o i n g r o u t i n e m ( s )( p c h ) ( s ) ( s ) 1 m ( s )( p c l ) e x e c u t e r t s (pc l )m (s) (s) (s) 1 ( s ) ( s ) + 1 (s) (s) + 1 ( p c h )m ( s ) s u b r o u t i n e p o p re t u r n a d d r e s s f r o m s t a c k p u s h r e t u r n a d d r e s s o n s t a c k m (s) (ps) execute rti ( p s )m ( s ) (s) (s) 1 (s) (s) + 1 i n t e r r u p t s e r v i c e r o u t i n e pop contents of processor status register from stack m (s) (pc h ) (s) (s) 1 m ( s )( p c l ) ( s ) ( s ) 1 (pc l )m (s) (s) (s) + 1 (s) (s) + 1 (pc h )m (s) p o p r e t u r n a d d r e s s f r o m s t a c k i flag is set from 0 to 1 fetch the jump vector p u s h r e t u r n a d d r e s s o n s t a c k p u s h c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r o n s t a c k i n t e r r u p t r e q u e s t ( n o t e ) i n t e r r u p t d i s a b l e f l a g i s 0
8 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group [processor status register (ps)] the processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide mcu operation. branch opera- tions can be performed by testing the carry (c) flag , zero (z) flag, overflow (v) flag, or the negative (n) flag. in decimal mode, the z, v, n flags are not valid. bit 0: carry flag (c) the c flag contains a carry or borrow generated by the arithmetic logic unit (alu) immediately after an arithmetic operation. it can also be changed by a shift or rotate instruction. bit 1: zero flag (z) the z flag is set if the result of an immediate arithmetic operation or a data transfer is 0 , and cleared if the result is anything other than 0 . bit 2: interrupt disable flag (i) the i flag disables all interrupts except for the interrupt generated by the brk instruction. interrupts are disabled when the i flag is 1 . bit 3: decimal mode flag (d) the d flag determines whether additions and subtractions are executed in binary or decimal. binary arithmetic is executed when this flag is 0 ; decimal arithmetic is executed when it is 1 . decimal correction is automatic in decimal mode. only the adc bit 4: break flag (b) the b flag is used to indicate that the current interrupt was generated by the brk instruction. the brk flag in the processor status register is always 0 . when the brk instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to 1 . bit 5: index x mode flag (t) when the t flag is 0 , arithmetic operations are performed between accumulator and memory. when the t flag is 1 , direct arithmetic operations and direct data transfers are enabled between memory locations. bit 6: overflow flag (v) the v flag is used during the addition or subtraction of one byte of signed data. it is set if the result exceeds +127 to -128. when the bit instruction is executed, bit 6 of the memory location operated on by the bit instruction is stored in the overflow flag. bit 7: negative flag (n) the n flag is set if the result of an arithmetic operation or data transfer is negative. when the bit instruction is executed, bit 7 of the memory location operated on by the bit instruction is stored in the negative flag. table 4 set and clear instructions of each bit of processor status register set instruction clear instruction c flag sec clc z flag i flag sei cli d flag sed cld b flag t flag set clt v flag clv n flag
9 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group [cpu mode register (cpum)] 003b 16 the cpu mode register contains the stack page selection bit and the internal system clock selection bit. the cpu mode register is allocated at address 003b 16 . fig. 7 structure of cpu mode register p rocessor mo d e bi ts b1 b0 0 0 : single-chip mode 01 : 1 0 : not available 11 : stack page selection bit 0 : 0 page 1 : 1 page not used (returns 1 when read) (do not write 0 to this bit) not used (returns 0 when read) (do not write 1 to this bit) system clock selection bit 0 : main clock (x in ) 1 : f syn system clock division ratio selection bits b7 b6 00 : = f(system clock)/8 (8-divide mode) 01 : = f(system clock)/4 (4-divide mode) 10 : = f(system clock)/2 (2-divide mode) 11 : = f(system clock) (through mode) cpu mo d e reg i ster (cpum : a dd ress 003 b 16 ) b 7 b 0 1 0
10 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group memory special function register (sfr) area the special function register area in the zero page contains con- trol registers such as i/o ports and timers. ram ram is used for data storage and for stack area of subroutine calls and interrupts. rom the first 128 bytes and the last 2 bytes of rom are reserved for device testing and the rest is user area for storing programs. in the flash memory version, program and erase can be performed in the reserved area. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page the 256 bytes from addresses 0000 16 to 00ff 16 are called the zero page area. the internal ram and the special function regis- ters (sfr) are allocated to this area. the zero page addressing mode can be used to specify memory and register addresses in the zero page area. access to this area with only 2 bytes is possible in the zero page addressing mode. special page the 256 bytes from addresses ff00 16 to ffff 16 are called the special page area. the special page addressing mode can be used to specify memory addresses in the special page area. ac- cess to this area with only 2 bytes is possible in the special page addressing mode. fig. 8 memory map diagram 192 256 384 512 640 768 896 1024 1536 2048 0 0 f f 1 6 0 1 3 f 1 6 0 1 b f 1 6 0 2 3 f 1 6 0 2 b f 1 6 0 3 3 f 1 6 0 3 b f 1 6 0 4 3 f 1 6 0 6 3 f 1 6 0 8 3 f 1 6 r a m a r e a r a m s i z e ( b y t e s ) a d d r e s s x x x x 1 6 4 0 9 6 8 1 9 2 1 2 2 8 8 1 6 3 8 4 2 0 4 8 0 2 4 5 7 6 2 8 6 7 2 3 2 7 6 8 3 6 8 6 4 4 0 9 6 0 4 5 0 5 6 4 9 1 5 2 5 3 2 4 8 5 7 3 4 4 6 1 4 4 0 f 0 0 0 1 6 e 0 0 0 1 6 d 0 0 0 1 6 c 0 0 0 1 6 b 0 0 0 1 6 a 0 0 0 1 6 9 0 0 0 1 6 8 0 0 0 1 6 7 0 0 0 1 6 6 0 0 0 1 6 5 0 0 0 1 6 4 0 0 0 1 6 3 0 0 0 1 6 2 0 0 0 1 6 1 0 0 0 1 6 f 080 16 e080 16 d080 16 c080 16 b080 16 a080 16 9080 16 8080 16 7080 16 6080 16 5080 16 4080 16 3080 16 2080 16 1080 16 rom area r o m s i z e ( b y t e s ) a d d r e s s y y y y 1 6 add ress zzzz 16 0100 16 0 0 0 0 1 6 0 0 4 0 1 6 0 fe 0 16 ff 00 16 f f d c 1 6 f f f e 1 6 ffff 16 xxxx 16 y y y y 1 6 zzzz 16 ram r o m sfr area n o t u s e d i nterrupt vector are a r eserve d rom area (128 bytes) z ero page s p e c i a l p a g e r e s e r v e d r o m a r e a 0 fff 16 s f r a r e a
11 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group fig. 9 memory map of special function register (sfr) 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 0 0 2 a 1 6 0 0 2 b 1 6 002 c 16 002 d 16 0 0 2 e 1 6 0 0 2 f 1 6 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 0 0 3 a 1 6 003 b 16 003 c 16 003 d 16 003 e 16 003 f 16 0 0 0 0 1 6 0001 16 0 0 0 2 1 6 0 0 0 3 1 6 0004 16 0 0 0 5 1 6 0006 16 0007 16 0 0 0 8 1 6 0 0 0 9 1 6 0 0 0 a 1 6 0 0 0 b 1 6 0 0 0 c 1 6 0 0 0 d 1 6 0 0 0 e 1 6 000 f 16 0010 16 0 0 1 1 1 6 0 0 1 2 1 6 0 0 1 3 1 6 0014 16 0015 16 0 0 1 6 1 6 0 0 1 7 1 6 0 0 1 8 1 6 0019 16 0 0 1 a 1 6 0 0 1 b 1 6 001 c 16 001 d 16 0 0 1 e 1 6 001 f 16 p o r t p 0 ( p 0 ) p o r t p 1 ( p 1 ) p o r t p 1 d i r e c t i o n r e g i s t e r ( p 1 d ) p o r t p 2 ( p 2 ) p o r t p 2 d i r e c t i o n r e g i s t e r ( p 2 d ) p o r t p 3 ( p 3 ) p o r t p 4 ( p 4 ) p o r t p 4 d i r e c t i o n r e g i s t e r ( p 4 d ) p o r t p 5 ( p 5 ) p ort p 5 di rect i on reg i ster (p 5 d) p ort p 6 (p 6 ) p o r t p 6 d i r e c t i o n r e g i s t e r ( p 6 d ) s er i a l i / o status reg i ster (siosts) i nterrupt contro l reg i ster 2 (icon 2 ) t ransm i t/ r ece i ve b u ff er reg i ster (tb/rb) cpu mo d e reg i ster (cpum) i nterrupt request reg i ster 1 (ireq 1 ) i nterrupt request reg i ster 2 (ireq 2 ) i nterrupt contro l reg i ster 1 (icon 1 ) p resca l er 12 (pre 12 ) ti mer 2 (t 2 ) p resca l er x (prex) ti mer x (tx) ti mer 1 (t 1 ) ti mer x mo d e reg i ster (tm) a - d contro l reg i ster (adcon) a - d convers i on reg i ster l ow (adl) p o r t p 0 d i r e c t i o n r e g i s t e r ( p 0 d ) p o r t p 3 d i r e c t i o n r e g i s t e r ( p 3 d ) r e s e r v e d ( n o t e ) r e s e r v e d ( n o t e ) usb contro l reg i ster (usbcon) u s b a d d r e s s e n a b l e r e g i s t e r ( u s b a e ) u s b a d d r e s s 0 r e g i s t e r ( u s b a 0 ) usb a dd ress 1 reg i ster (usba 1 ) e n d p o i n t i n d e x r e g i s t e r ( u s b i n d e x ) e n d p o i n t f i e l d r e g i s t e r 1 ( e p x x r e g 1 ) e n d po i nt fi e ld reg i ster 2 (epxxreg 2 ) e n d po i nt fi e ld reg i ster 3 (epxxreg 3 ) e n d p o i n t f i e l d r e g i s t e r 4 ( e p x x r e g 4 ) e n d p o i n t f i e l d r e g i s t e r 5 ( e p x x r e g 5 ) e n d p o i n t f i e l d r e g i s t e r 6 ( e p x x r e g 6 ) e n d po i nt fi e ld reg i ster 7 (epxxreg 7 ) r e s e r v e d ( n o t e ) r eserve d (n ote ) f r a m e n u m b e r r e g i s t e r l o w ( f n u m l ) f r a m e n u m b e r r e g i s t e r h i g h ( f n u m h ) u s b i n t e r r u p t s o u r c e e n a b l e r e g i s t e r ( u s b i c o n ) u s b i n t e r r u p t s o u r c e r e g i s t e r ( u s b i r e q ) e x b i n t e r r u p t s o u r c e e n a b l e r e g i s t e r ( e x b i c o n ) e xb i n t e r r u p t s o u r c e r e g i s t e r ( e x b i r e q ) r e s e r v e d ( n o t e ) e x b i n d e x r e g i s t e r ( e x b i n d e x ) r eg i ster w i n d ow 1 (exbreg 1 ) r e g i s t e r w i n d o w 2 ( e x b r e g 2 ) a - d convers i on reg i ster hi g h (adh) watchdog timer control register (wdtcon) r e s e r v e d ( n o t e ) 0 f e 0 1 6 0 f e 1 1 6 0 fe 2 16 0 fe 3 16 0 f e 4 1 6 0 f e 5 1 6 0 f e 6 1 6 0 f e 7 1 6 0 f e 8 1 6 0 fe 9 16 0 f e a 1 6 fl as h memory contro l reg i ster (fmcr) p l l c o n t r o l r e g i s t e r ( p l l c o n ) p ort p 5 pu ll -up contro l reg i ster (pull 5 ) e n d p o i n t f i e l d r e g i s t e r 8 ( e p x x r e g 8 ) e n d p o i n t f i e l d r e g i s t e r 9 ( e p x x r e g 9 ) s e r i a l i / o c o n t r o l r e g i s t e r ( s i o c o n ) u a r t c o n t r o l r e g i s t e r ( u a r t c o n ) b a u d r a t e g e n e r a t o r ( b r g ) p o r t p 0 p u l l - u p c o n t r o l r e g i s t e r ( p u l l 0 ) interrupt edge selection register (intedge) r e s e r v e d ( n o t e ) 0 feb 16 0 f e c 1 6 0 f e d 1 6 0 fee 16 0 f e f 1 6 0 ff 0 16 0 ff 1 16 0 ff 2 16 0 ff 3 16 0 ff 4 16 0 ff 5 16 0 ff 6 16 0 ff 7 16 0 ff 8 16 0 ff 9 16 0 ffa 16 0 ffb 16 0 ffc 16 0 ffd 16 0 ffe 16 0 fff 16 r e s e r v e d ( n o t e ) r e s e r v e d ( n o t e ) r e s e r v e d ( n o t e ) r eserve d (n ote ) r e s e r v e d ( n o t e ) r e s e r v e d ( n o t e ) r eserve d (n ote ) r e s e r v e d ( n o t e ) r e s e r v e d ( n o t e ) r e s e r v e d ( n o t e ) r eserve d (n ote ) r e s e r v e d ( n o t e ) r e s e r v e d ( n o t e ) r eserve d (n ote ) r eserve d (n ote ) m i s r g r e s e r v e d ( n o t e ) r e s e r v e d ( n o t e ) r eserve d (n ote ) r eserve d (n ote ) n ote : d o not wr i te any d ata to t h ese a dd resses, b ecause t h ese areas are reserve d . hub interrupt source enable register (hubicon) h ub i n t e r r u p t s o u r c e r e g i s t e r ( h u b i r e q ) h u b d o w n s t r e a m p o r t i n d e x r e g i s t e r ( h u b i n d e x ) h u b p o r t f i e l d r e g i s t e r 1 ( d p x r e g 1 ) h u b p o r t f i e l d r e g i s t e r 2 ( d p x r e g 2 ) h u b p o r t f i e l d r e g i s t e r 3 ( d p x r e g 3 ) d o w n s t r e a m p o r t c o n t r o l r e g i s t e r ( d p c t l )
12 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group i/o ports the i/o ports have direction registers which determine the input/ output direction of each individual pin. each bit in a direction reg- ister corresponds to one pin, and each pin can be set to be input port or output port. when 0 is written to the bit corresponding to a pin, that pin be- comes an input pin. when 1 is written to that bit, that pin be- comes an output pin. if data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. pins set to input are floating. if a pin set to input is written to, only the port output latch is written to and the pin remains floating. table 5 i/o ports functions related sfrs port p0 pull-up control register a-d control register exb control register exb control register exb control register serial i/o control register exb control register serial i/o control register exb control register serial i/o control register exb control register serial i/o control register exb control register port p5 pull-up control register interrupt edge selection register timer x mode register input/output input/output, individual bits name port p0 port p1 port p2 port p3 port p4 port p5 port p6 pin p0 0 p0 7 p1 0 p1 7 p2 4 p2 7 p3 0 p3 2 p3 3 /e x int p3 4 /e x cs p3 5 /e x wr p3 6 /e x rd p3 7 /e x a0 p4 0 /rxd/ exdreq p4 1 /txd/ exdack p4 2 /s clk / extc p4 3 /s rdy / exa1 p5 0 /int 0 p5 2 /int 1 p5 1 /cntr 0 p5 3 p5 7 p6 0 p6 3 non-port function key-on wake up a-d conversion input external bus interface funciton i/o external bus interface funciton output external bus interface funciton input serial i/o input external bus interface funciton output serial i/o output external bus interface funciton input serial i/o i/o external bus interface funciton input serial i/o output external bus interface funciton input external interrupt input timer x function i/o i/o format cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output (power source is v cc e) cmos compatible input level cmos 3-state output cmos/ttl compat- ible input level cmos 3-state output (power source is vcce) cmos compatible input level cmos 3-state output diagram no. (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) note: make sure that the input level at each pin is either 0 v or v cc during execution of the stp instruction. when an input level is at an intermediate poten- tial, a current will flow from v cc to v ss through the input-stage gate.
13 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group fig. 10 port block diagram (1) (4) ports p3 0 p3 2 ( 1 ) p o r t p 0 d a t a b u s p o r t l a t c h k e y - o n w a k e - u p i n p u t p u l l - u p c o n t r o l b i t ( 5 ) p o r t p 3 3 e x i n t o u t p u t ( 6 ) p o r t s p 3 4 , p 3 5 , p 3 6 , p 3 7 e x c s ( p 3 4 ) e x w r ( p 3 5 ) e x r d ( p 3 6 ) e x a 0 ( p 3 7 ) ( 2 ) p o r t p 1 a n a l o g i n p u t p i n s e l e c t i o n b i t a - d c o n v e r s i o n i n p u t e x o e e x t e r n a l b u s i n t e r f a c e e n a b l e b i t o u t p u t b u f f e r i n p u t b u f f e r ( 3 ) p o r t p 2 d i r e c t i o n r e g i s t e r e x b d a t a o u t p u t e x b d a t a i n p u t v c c e v c c e v c c e v c c e d a t a b u s p o r t l a t c h d i r e c t i o n r e g i s t e r d a t a b u s p o r t l a t c h d i r e c t i o n r e g i s t e r d a t a b u sp o r t l a t c h d i r e c t i o n r e g i s t e r e x t e r n a l b u s i n t e r f a c e e n a b l e b i t p o r t l a t c h d a t a b u s d i r e c t i o n r e g i s t e r e x t e r n a l b u s i n t e r f a c e e n a b l e b i t e x t e r n a l b u s i n t e r f a c e e n a b l e b i t d a t a b u sp o r t l a t c h d i r e c t i o n r e g i s t e r
14 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group fig. 11 port block diagram (2) e x d r e q o u t p u t s e r i a l i / o i n p u t e x dac k s e r i a l i / o e n a b l e b i t e x tc serial i/o synchronous clock selection bit e x a1 cntr 0 interrupt input pulse output mode i n t 0 ( p 5 0 ) , i n t 1 ( p 5 2 ) i n t e r r u p t i n p u t v c c e v c c e v cc e v c c e s rdy output enable bit (7) port p4 0 d i r e c t i o n r e g i s t e r direction register direction register direction register p o r t l a t c h p o r t l a t c h p o r t l a t c h p o r t l a t c h port latch p o r t l a t c h port latch port latch direction register d i r e c t i o n r e g i s t e r d i r e c t i o n r e g i s t e r d i r e c t i o n r e g i s t e r data bus d a t a b u s data bus d a t a b u s d a t a b u s data bus data bus data bus serial i/o output (8) port p4 1 (9) port p4 2 (10) port p4 3 ( 1 1 ) p o r t s p 5 0 , p 5 2 ( 1 2 ) p o r t p 5 1 (13) ports p5 3 p5 7 ( 1 4 ) p o r t p 6 serial i/o enable bit s e r i a l i / o e n a b l e b i t s e r i a l i / o e n a b l e b i t external bus interface enable bit e x t e r n a l b u s i n t e r f a c e e n a b l e b i t e x t e r n a l b u s i n t e r f a c e e n a b l e b i t e x t e r n a l b u s i n t e r f a c e e n a b l e b i t external bus interface enable bit e x t e r n a l b u s i n t e r f a c e e n a b l e b i t external bus interface enable bit r e c e i v e e n a b l e b i t receive enable bit pull-up control bit serial i/o mode selection bit serial i/o mode selection bit timer output serial i/o synchronous clock selection bit serial i/o output serial i/o external clock input s e r i a l i / o c l o c k o u t p u t s e r i a l i / o e n a b l e b i t
15 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group fig. 12 structure of port i/o-related registers p 0 0 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 0 1 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 0 2 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 0 3 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 0 4 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 0 5 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 0 6 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 0 7 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p o r t p 0 p u l l - u p c o n t r o l r e g i s t e r ( p 0 p u l l : a d d r e s s 0 f f 0 1 6 ) b 7 b 0 p 5 0 pu ll -up contro l bi t 0 : no pull-up 1 : pull-up nothing is arranged for this bit. this is a write disabled bit. when this bit is read out, the contents are 0 . p5 2 pull-up control bit 0 : no pull-up 1 : pull-up nothing is arranged for these bits. these are write disabled bits. when these bits are read out, the contents are 0 . p o r t p 5 p u l l - u p c o n t r o l r e g i s t e r ( p 5 p u l l : a d d r e s s 0 f f 2 1 6 ) b 7 b 0
16 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group interrupt request generating conditions at reset at detection of usb bus reset signal (2.5 s interval se0) at detection of usb sof signal at detection of resume signal (k state or se0) or suspend signal (3 ms interval bus idle), or at completion of transaction at completion of reception or transmission or at completion of dma transmission at detection of either rising or falling edge of int 0 input at timer x underflow at timer 1 underflow at timer 2 underflow at detection of either rising or falling edge of int 1 input at detection of usb hub downport s state switch at completion of serial i/o data reception at completion of serial i/o data transmission at detection of either rising or falling edge of cntr 0 input at falling of conjunction of input level for port p2 (at input mode) at completion of a-d conversion at brk instruction execution notes 1 : vector addresses contain interrupt jump destination addresses. 2 : reset function in the same way as an interrupt with the highest priority. interrupts i nterrupts occur by sixteen sources: four external, eleven internal, and one software. interrupt control each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software in- terrupt set by the brk instruction. an interrupt occurs if the corre- sponding interrupt request and enable bits are 1 and the inter- rupt disable flag is 0 . interrupt enable bits can be set or cleared by software. interrupt request bits can be cleared by software, but cannot be set by software. the brk instruction cannot be disabled with any flag or bit. the i flag disables all interrupts except the brk instruction interrupt. when several interrupts occur at the same time, the interrupts are received according to priority. interrupt operation by acceptance of an interrupt, the following operations are auto- matically performed: 1. the contents of the program counter and the processor status register are automatically pushed onto the stack. 2. the interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. the interrupt jump destination address is read from the vector table into the program counter. interrupt source reset (note 2) usb bus reset usb sof usb device external bus int 0 timer x timer 1 timer 2 int 1 usb hub serial i/o reception serial i/o transmission cntr 0 key-on wake up a-d conversion brk instruction low fffc 16 fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 ffdc 16 high fffd 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdd 16 table 6 interrupt vector addresses and priority priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 vector addresses (note 1) notes on interrupts when setting the followings, the interrupt request bit may be set to 1 . when setting external interrupt active edge related register: interrupt edge selection register (address 0ff3 16 ), timer x mode register (address 0023 16 ) when not requiring for the interrupt occurrence synchronized with these setting, take the following sequence. ? set the corresponding interrupt enable bit to 0 (disabled). ? set the interrupt edge select bit (active edge switch bit). ? set the corresponding interrupt request bit to 0 after 1 or more instructions have been executed. ? set the corresponding interrupt enable bit to 1 (enabled).
17 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group fig. 13 interrupt control fig. 14 structure of interrupt-related registers i n t e r r u p t r e q u e s t b i t i n t e r r u p t e n a b l e b i t interrupt disable flag (i) b r k i n s t r u c t i o n r e s e t i n t e r r u p t r e q u e s t b 7 b 0 i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r i n t 0 i n t e r r u p t e d g e s e l e c t i o n b i t n o t u s e d ( r e t u r n 0 w h e n r e a d ) i n t 1 i n t e r r u p t e d g e s e l e c t i o n b i t n o t u s e d ( r e t u r n 0 w h e n r e a d ) ( i n t e d g e : a d d r e s s 0 f f 3 1 6 ) i n t e r r u p t r e q u e s t r e g i s t e r 1 usb b us reset i nterrupt request bi t usb sof interrupt request bit usb device interrupt request bit exb interrupt request bit int 0 interrupt request bit timer x interrupt request bit timer 1 interrupt request bit timer 2 interrupt request bit i n t e r r u p t c o n t r o l r e g i s t e r 1 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d (ireq 1 : a dd ress 003 c 16 ) (icon 1 : a dd ress 003 e 16 ) i nterrupt request reg i ster 2 int 1 i nterrupt request bi t usb hub interrupt request bit serial i/o receive interrupt request bit serial i/o transmit interrupt request bit cntr 0 interrupt request bit key-on wake-up interrupt request bit a-d conversion interrupt request bit nothing is arranged for this bit. this is a write disabled bit. when this bit is read out, the contents are 0 . (ireq 2 : a dd ress 003 d 16 ) i n t e r r u p t c o n t r o l r e g i s t e r 2 0 : i n t e r r u p t s d i s a b l e d 1 : i n t e r r u p t s e n a b l e d (icon 2 : a dd ress 003 f 16 ) 0 : f a lli ng e d ge act i ve 1 : rising edge active b 7 b 0 b 7 b 0 b 7 b 0 b 7 b 0 usb b us reset i nterrupt ena bl e bi t usb sof interrupt enable bit usb device interrupt enable bit exb interrupt enable bit int 0 interrupt enable bit timer x interrupt enable bit timer 1 interrupt enable bit timer 2 interrupt enable bit int 1 i nterrupt ena bl e bi t usb hub interrupt enable bit serial i/o receive interrupt enable bit serial i/o transmit interrupt enable bit cntr 0 interrupt enable bit key-on wake-up interrupt enable bit a-d conversion interrupt enable bit fix this bit to 0 . ? 0 c a n b e s e t b y s o f t w a r e , b u t 1 c a n n o t b e s e t . ? 0 can be set by software, but 1 cannot be set.
18 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group key input interrupt (key-on wake up) a key-on wake up interrupt request is generated by applying a falling edge to any pin of port p0 that have been set to input mode. in other words, it is generated when and of input level goes from 1 to 0 . an example of using a key input interrupt is shown in figure 15, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports p0 0 p0 3 . fig. 15 connection example when using key input interrupt and port p0 block diagram ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? p o r t p 0 0 l a t c h port p0 0 direction register = 0 port p0 1 latch port p0 1 direction register = 0 p o r t p 0 2 l a t c h port p0 2 direction register = 0 p o r t p 0 3 l a t c h port p0 3 direction register = 0 p o r t p 0 4 l a t c h port p0 4 direction register = 1 p o r t p 0 5 l a t c h port p0 5 direction register = 1 p o r t p 0 6 l a t c h port p0 6 direction register = 1 p o r t p 0 7 l a t c h port p0 7 direction register = 1 p 0 0 i n p u t p 0 1 i n p u t p0 2 input p 0 3 i n p u t p 0 4 o u t p u t p 0 5 o u t p u t p 0 6 o u t p u t p 0 7 o u t p u t p u l l 0 r e g i s t e r b i t 7 = 0 p o r t p 0 i n p u t r e a d i n g c i r c u i t p o r t p x x l l e v e l o u t p u t ? p-channel transistor for pull-up ? ? cmos output buffer key input interrupt request p u l l 0 r e g i s t e r b i t 6 = 0 pull 0 register bit 5 = 0 p u l l 0 r e g i s t e r b i t 4 = 0 pull 0 register bit 3 = 1 p u l l 0 r e g i s t e r b i t 2 = 1 pull 0 register bit 1 = 1 pull 0 register bit 0 = 1
19 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group timers the 38k0 group has three timers: timer x, timer 1, and timer 2. the division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. all timers are down count timers. when the timer reaches 00 16 , an underflow occurs at the next count pulse and the correspond- ing timer latch is reloaded into the timer and the count is contin- ued. when a timer underflows, the interrupt request bit corre- sponding to that timer is set to 1 . fig. 16 structure of timer x mode register timer 1 and timer 2 the count source of prescaler 12 is the system clock divided by 16. the output of prescaler 12 is counted by timer 1 and timer 2, and a timer underflow periodically sets the interrupt request bit. timer x timer x can each select in one of four operating modes by setting the timer x mode register. (1) timer mode the timer counts the count source selected by timer count source selection bit. (2) pulse output mode the timer counts the system clock divided by 16. whenever the contents of the timer reach 00 16 , the signal output from the cntr 0 pin is inverted. if the cntr 0 active edge selection bit is 0 , output begins at h . if it is 1 , output starts at l . when using a timer in this mode, set the corresponding port p5 1 direction register to output mode. (3) event counter mode operation in event counter mode is the same as in timer mode, except that the timer counts signals input through the cntr 0 pin. when the cntr 0 active edge selection bit is 0 , the rising edge of the cntr 0 pin is counted. when the cntr 0 active edge selection bit is 1 , the falling edge of the cntr 0 pin is counted. (4) pulse width measurement mode if the cntr 0 active edge selection bit is 0 , the timer counts the system clock divided by 16 while the cntr 0 pin is at h . if the cntr 0 active edge selection bit is 1 , the timer counts it while the cntr 0 pin is at l . the count can be stopped by setting 1 to the timer x count stop bit in any mode. the corresponding interrupt request bit is set each time a timer underflows. t i m e r x m o d e r e g i s t e r ( t m : a d d r e s s 0 0 2 3 1 6 ) ti mer x operat i ng mo d e bi ts b1 b0 0 0 : timer mode 0 1 : pulse output mode 1 0 : event counter mode 1 1 : pulse width measurement mode cntr 0 active edge switch bit 0 : falling edge active for cntr 0 interrupt count at rising edge in event counter mode 1 : rising edge active for cntr 0 interrupt count at falling edge in event counter mode timer x count stop bit 0 : count start 1 : count stop not used (return 0 when read) b 7 b 0
20 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group fig. 17 timer block diagram q q 1 0 p 5 1 / c n t r 0 1 / 1 6 0 1 r t s y s t e m c l o c k 1 / 1 6 p r e s c a l e r x l a t c h ( 8 ) prescaler x (8) timer x latch (8) timer x (8) t i m e r x i n t e r r u p t r e q u e s t b i t toggle flip-flop t i m e r x c o u n t s t o p b i t p u l s e w i d t h m e a s u r e m e n t m o d e e v e n t c o u n t e r m o d e c n t r 0 i n t e r r u p t r e q u e s t b i t p u l s e o u t p u t m o d e p o r t p 5 1 l a t c h port p5 1 direction register cntr 0 active edge selection bit timer x latch write pulse output mode timer mode pulse output mode d a t a b u s d i v i d e r prescaler 12 latch (8) p r e s c a l e r 1 2 ( 8 ) timer 1 latch (8) timer 1 (8) timer 2 latch (8) timer 2 (8) t i m e r 2 i n t e r r u p t r e q u e s t b i t t i m e r 1 i n t e r r u p t r e q u e s t b i t c n t r 0 a c t i v e e d g e s e l e c t i o n b i t data bus s y s t e m c l o c k d i v i d e r
21 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group serial i/o serial i/o can be used as either clock synchronous or asynchro- nous (uart) serial i/o. a dedicated timer (baud rate generator) is also provided for baud rate generation. (1) clock synchronous serial i/o mode clock synchronous serial i/o mode can be selected by setting the mode selection bit of the serial i/o control register (bit 6 of ad- dress 0fe0 16 ) to 1 . for clock synchronous serial i/o, the transmitter and the receiver must use the same clock. if an internal clock is used, transfer is started by a write signal to the trancemit/receive buffer register. fig. 18 block diagram of clock synchronous serial i/o fig. 19 operation of clock synchronous serial i/o function p 4 2 / e x t c / s c l k p 4 3 / e x a 1 / s r d y p 4 0 / e x d r e q / r x d s y s t e m c l o c k 1/4 1 / 4 f / f serial i/o status registe r s e r i a l i / o c o n t r o l r e g i s t e r r e c e i v e b u f f e r r e g i s t e r a d d r e s s 0 0 2 6 1 6 r e c e i v e s h i f t r e g i s t e r r e c e i v e b u f f e r f u l l f l a g ( r b f ) r ece i ve i nterrupt request (ri) clock control circuit s h i f t c l o c k s e r i a l i / o s y n c h r o n o u s c l o c k s e l e c t i o n b i t f r e q u e n c y d i v i s i o n r a t i o 1 / ( n + 1 ) b a u d r a t e g e n e r a t o r add ress 0 fe 2 16 b r g c o u n t s o u r c e s e l e c t i o n b i t clock control circuit f a l l i n g - e d g e d e t e c t o r d ata b us add ress 0026 16 shif t c l oc k t r a n s m i t s h i f t r e g i s t e r s h i f t c o m p l e t i o n f l a g ( t s c ) t ransm i t b u ff er empty fl ag (tbe) t ransm i t i nterrupt request (ti) t ransm i t i nterrupt source se l ect i on bi t add ress 0027 16 d ata b us a d d r e s s 0 f e 0 1 6 transmit buffer register transmit shift register p 4 1 / e x dack / t x d r e c e i v e e n a b l e s i g n a l s r d y d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 r b f = 1 t s c = 1 t b e = 0 t b e = 1 t s c = 0 t rans f er s hif t c l oc k (1/2 to 1/2048 of the internal clock, or an external clock) s e r i a l o u t p u t t x d s e r i a l i n p u t r x d w r i te s i gna l to rece i ve/transm i t buffer register (address 0026 16 ) o verrun error (oe) detection n o t e s 1 : t h e t r a n s m i t i n t e r r u p t ( t i ) c a n b e g e n e r a t e d e i t h e r w h e n t h e t r a n s m i t b u f f e r r e g i s t e r h a s e m p t i e d ( t b e = 1 ) o r a f t e r t h e t r a n s m i t s h i f t o p e r a t i o n h a s e n d e d ( t s c = 1 ) , b y s e t t i n g t h e t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) o f t h e s e r i a l i / o 1 c o n t r o l r e g i s t e r . 2 : i f d a t a i s w r i t t e n t o t h e t r a n s m i t b u f f e r r e g i s t e r w h e n t s c = 0 , t h e t r a n s m i t c l o c k i s g e n e r a t e d c o n t i n u o u s l y a n d s e r i a l d a t a i s o u t p u t c o n t i n u o u s l y f r o m t h e t x d p i n . 3 : t h e r e c e i v e i n t e r r u p t ( r i ) i s s e t w h e n t h e r e c e i v e b u f f e r f u l l f l a g ( r b f ) b e c o m e s 1 . d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6
22 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group (2) asynchronous serial i/o (uart) mode clock asynchronous serial i/o mode (uart) can be selected by setting the serial i/o mode selection bit of the serial i/o control register to 0 . eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. the transmit and receive shift registers each have a buffer regis- ter, but the two buffers have the same address in memory. since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. the transmit buffer can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. fig. 20 block diagram of uart serial i/o fig. 21 operation of uart serial i/o function s y s t e m c l o c k 1 / 4 oe pe f e 1 / 1 6 1/16 d a t a b u s r ece i ve b u ff er reg i ster add ress 0026 16 r ece i ve s hif t reg i ster r e c e i v e b u f f e r f u l l f l a g ( r b f ) r e c e i v e i n t e r r u p t r e q u e s t ( r i ) b a u d r a t e g e n e r a t o r f r e q u e n c y d i v i s i o n r a t i o 1 / ( n + 1 ) add ress 0 fe 2 16 st/sp/pa generator transmit buffer register d ata b us t ransm i t s hif t reg i ster add ress 0026 16 t ransm i t s hif t reg i ster s hif t comp l et i on fl ag (tsc) t ransm i t b u ff er empty fl ag (tbe) t ransm i t i nterrupt request (ti) add ress 0027 16 s t d e t e c t o r sp d etector uart contro l reg i ster add ress 0 fe 1 16 ch aracter l engt h se l ect i on bi t a d d r e s s 0 f e 0 1 6 brg count source se l ect i on bit t ransm i t i nterrupt source se l ect i on bit s er i a l i / o sync h ronous c l oc k se l ect i on bi t cl oc k contro l c i rcu i t c h a r a c t e r l e n g t h s e l e c t i o n b i t 7 b i t s 8 b i t s s er i a l i / o 1 contro l reg i ster p 4 2 / e x t c / s c l k s er i a l i / o status reg i ster p 4 0 / e x d r e q / r x d p 4 1 / e x dack / t x d t s c = 0 t b e = 1 r b f = 0 t b e = 0 t b e = 0 r b f = 1 r b f = 1 s t d 0 d 1 s p d 0 d 1 s t s p t b e = 1 t s c = 1 ? s t d 0 d 1 s p d 0 d 1 s t s p t r a n s m i t b u f f e r w r i t e s i g n a l ? g e n e r a t e d a t 2 n d b i t i n 2 - s t o p - b i t m o d e 1 s t a r t b i t 7 o r 8 d a t a b i t s 1 o r 0 p a r i t y b i t 1 o r 2 s t o p b i t ( s ) 1 : e r r o r f l a g d e t e c t i o n o c c u r s a t t h e s a m e t i m e t h a t t h e r b f f l a g b e c o m e s 1 ( a t 1 s t s t o p b i t , d u r i n g r e c e p t i o n ) . 2 : t h e t r a n s m i t i n t e r r u p t ( t i ) c a n b e g e n e r a t e d t o o c c u r w h e n e i t h e r t h e t b e o r t s c f l a g b e c o m e s 1 , d e p e n d i n g o n t h e s e t t i n g o f t h e t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) o f t h e s e r i a l i / o 1 c o n t r o l r e g i s t e r . 3 : t h e r e c e i v e i n t e r r u p t ( r i ) i s s e t w h e n t h e r b f f l a g b e c o m e s 1 . 4 : a f t e r d a t a i s w r i t t e n t o t h e t r a n s m i t b u f f e r r e g i s t e r w h e n t s c = 1 , 0 . 5 t o 1 . 5 c y c l e s o f t h e d a t a s h i f t c y c l e i s n e c e s s a r y u n t i l c h a n g i n g t o t s c = 0 . n o t e s s e r i a l o u t p u t t x d s e r i a l i n p u t r x d r e c e i v e b u f f e r r e a d s i g n a l t r a n s m i t o r r e c e i v e c l o c k
23 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group [serial i/o control register (siocon)] 0fe0 16 the serial i/o control register contains eight control bits for the se- rial i/o function. [uart control register (uartcon)] 0fe1 16 the uart control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial i/o is selected and set the data format of an data transfer. [serial i/o status register (siosts)] 0027 16 the read-only serial i/o status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is cleared to 0 when the receive buffer is read. if there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. a write to the serial i/o status register clears all the error flags oe, pe, fe, and se (bit 3 to bit 6, respectively). writing 0 to the serial i/o enable bit sioe (bit 7 of the serial i/o control register) also clears all the status flags, including the error flags. all bits of the serial i/o status register are initialized to 0 at reset, but if the transmit enable bit (bit 4) of the serial i/o control register has been set to 1 , the transmit shift register shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become 1 . [transmit buffer/receive buffer register (tb/ rb)] 0026 16 the transmit buffer register and the receive buffer register are lo- cated at the same address. the transmit buffer register is write- only and the receive buffer register is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer regis- ter is 0 . [baud rate generator (brg)] 0fe2 16 the baud rate generator determines the baud rate for serial trans- fer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate genera- tor. notes on serial i/o when setting the transmit enable bit to 1 , the serial i/o transmit interrupt request bit is automatically set to 1 . when not requiring the interrupt occurrence synchronized with the transmission enalbed, take the following sequence. ? set the serial i/o transmit interrupt enable bit to 0 (disabled). ? set the transmit enable bit to 1 . ? set the serial i/o transmit interrupt request bit to 0 after 1 or more instructions have been executed. ? set the serial i/o transmit interrupt enable bit to 1 (enabled).
24 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group fig. 22 structure of serial i/o control registers brg count source se l ect i on bi t (css) 0: system clock 1: system clock/4 serial i/o synchronous clock selection bit (scs) 0: brg output divided by 4 when clock synchronous serial i/o is selected. brg output divided by 16 when uart is selected. 1: external clock input when clock synchronous serial i/o is selected. external clock input divided by 16 when uart is selected. s rdy output enable bit (srdy) 0: p4 3 pin operates as ordinary i/o pin 1: p4 3 pin operates as s rdy output pin transmit interrupt source selection bit (tic) 0: interrupt when transmit buffer has emptied 1: interrupt when transmit shift operation is completed transmit enable bit (te) 0: transmit disabled 1: transmit enabled receive enable bit (re) 0: receive disabled 1: receive enabled serial i/o mode selection bit (siom) 0: asynchronous serial i/o (uart) 1: clock synchronous serial i/o serial i/o enable bit (sioe) 0: serial i/o disabled (pins p4 0 p4 3 operate as ordinary i/o pins) 1: serial i/o enabled (pins p4 0 p4 3 can operate as serial i/o pins) s e r i a l i / o c o n t r o l r e g i s t e r ( s i o c o n : a d d r e s s 0 f e 0 1 6 ) b7 b0 t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) 0 : b u f f e r f u l l 1 : b u f f e r e m p t y r e c e i v e b u f f e r f u l l f l a g ( r b f ) 0 : b u f f e r e m p t y 1 : b u f f e r f u l l t r a n s m i t s h i f t r e g i s t e r s h i f t c o m p l e t i o n f l a g ( t s c ) 0 : t r a n s m i t s h i f t i n p r o g r e s s 1 : t r a n s m i t s h i f t c o m p l e t e d o v e r r u n e r r o r f l a g ( o e ) 0 : n o e r r o r 1 : o v e r r u n e r r o r p a r i t y e r r o r f l a g ( p e ) 0 : n o e r r o r 1 : p a r i t y e r r o r f r a m i n g e r r o r f l a g ( f e ) 0 : n o e r r o r 1 : f r a m i n g e r r o r s u m m i n g e r r o r f l a g ( s e ) 0 : ( o e ) u ( p e ) u ( f e ) = 0 1 : ( o e ) u ( p e ) u ( f e ) = 1 n o t u s e d ( r e t u r n s 1 w h e n r e a d ) s er i a l i / o status reg i ster (siosts : address 0027 16 ) b 7b 0 u a r t c o n t r o l r e g i s t e r ( u a r t c o n : a d d r e s s 0 f e 1 1 6 ) c h a r a c t e r l e n g t h s e l e c t i o n b i t ( c h a s ) 0 : 8 b i t s 1 : 7 b i t s p a r i t y e n a b l e b i t ( p a r e ) 0 : p a r i t y c h e c k i n g d i s a b l e d 1 : p a r i t y c h e c k i n g e n a b l e d p a r i t y s e l e c t i o n b i t ( p a r s ) 0 : e v e n p a r i t y 1 : o d d p a r i t y s t o p b i t l e n g t h s e l e c t i o n b i t ( s t p s ) 0 : 1 s t o p b i t 1 : 2 s t o p b i t s n o t u s e d ( r e t u r n 0 w h e n r e a d ) ( t h i s i s a w r i t e d i s a b l e d b i t . ) n o t u s e d ( r e t u r n 1 w h e n r e a d ) b 7b 0
25 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group usb function 38k2 group is equipped with a usb function control circuit (usbfcc) that enables effective interfacing with the host-pc. this circuit is in compliance with usb specification version 2.0 full-speed transfer mode (12 mbps, equivalent to version 1.1). this circuit also supports all four transfer-types specified in the standard usb specification. the usbfcc has two usb addresses and 6 endpoints, enabling separate control of the hub functions and peripheral functions. the usb address for hub functions is equipped with two end- points. each endpoint is fixed to a specified transfer type: endpoint 0 is fixed to control transfer and endpoint 1 is fixed to interrupt transfer. the usb address for peripheral functions is equipped with four endpoints that can select its transfer type. although endpoint 0 is fixed to control transfer, the endpoints 1 to 3 can be set to inter- rupt transfer, bulk transfer, or isochronous transfer. a dedicated circuit automatically performs stage management for control transfer and packet management for transactions, which are necessary for matching of data transmit/receive timing, error detection, and retry after error. this dedicated control circuit en- ables the user to develop a program or timing design very easily. each endpoint can be programmed for data transfer conditions so that the endpoints are adaptive for all usb device class transfer systems. the data buffer of each endpoint can be assigned to any area in the multi-channel ram. this feature offers highly efficient memory usage by avoiding re-buffering and enabling simple data modifica- tion. the transmit/receive data is directly transferred to the data buffer via the control circuit (direct ram access type) without disturbing the cpu operation. this mechanism enables the cpu to transfer data smoothly with no drop in performance. in addition to this buffer function, a double-buffer setting will keep a re-buffering stall at a minimum and increase the overall data throughput (max. 64 bytes x 2 channels). as other special signals control, the endpoints have detection functions for the usb bus reset signal, resume signal, suspend signal, and sof signal, and also have a remote wake-up signal transmit function. when completing data transfer or receiving a special signal, the endpoint generates the corresponding interrupt to the cpu (3 vec- tors/24 factors). with all this essential yet comprehensive built-in hardware, your system using the 38k2 group will be ready for any usb applica- tion that comes its way. usb data transfer the usb specification promises 12 mbps data transfer in the full- speed mode, that is equivalent to 1.5 m bytes per second of data transactions. however, in usb data transfer, bit-stuffing may be executed de- pending on the bit patterns of the transfer data, possibly resulting in 1-byte data (normally 8 bits) handled as up to 10 bits. because usb uses asynchronous transfers, the clock cycle of the usb internal reference clock may change to adjust to the clock phase. therefore, the access timing of the usbfcc for the multi- channel ram will change owing to the frequency of internal clock : when the usbfcc is operating at =8 mhz, access for a normal transfer is performed every 5 to 6 cycles and access for a bit-stuff- ing transfer is performed in up to 7 cycles. if the exb function is enabled in the above conditions, this func- tion generates a maximum wait of 1 clock cycle, so that the access is performed every 4 to 8 cycles. when operating at = 6mhz, a normal access is performed every 4 cycles. if the clock-phase correction of the reference clock oc- curs, access is performed every 3 to 5 cycles. if bit stuffing occurs at this clock rate, the access cycle will be ex- tended to up to 6 cycles. when the exb function that generates a maximum 1-wait cycle is used in this condition, the access cycle will be 2 (min.) to 7 (max.) cycles. interrupt request data transmit/receive path [direct ram access type] 38k2 group mcu usb bus (usb-host) external mcu cpu program rom usb multi-channel ram built-in peripheral functions external bus interface (exb) fig. 23 usb function overview
26 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group usb function control circuit (usbfcc) block diagram the following diagram shows the usbfcc block diagram. the cir- cuit comprises: (1) serial interface engine (sie) (2) device control unit (dcu) (3) internal memory interface (mif) (4) cpu interface (cif) fig. 24 usb function control circuit (usbfcc) block diagram c p u c i f u s b f u n c t i o n c o n t r o l c i r c u i t d c u m i f s i e dcu control dcu status mif control sie control s i e s t a t u s transmit/receive data u s b t r a n s c e i v e r d 0 + d0- multi-channel ram (1) serial interface engine (sie) the sie performs the following usb lower-layer protocols (pack- ets, transactions): ?ampling of receive data and clock, generation of transmit clock ?erial-to-parallel conversion of transmit/receive data ?rzi (non return zero invert) encode/decode ?it stuffing/unstuffing ?ync (synchronization pattern) detection, eop (end of packet) detection ?sb address detection, endpoint detection ?rc (cyclic redundancy check) generation and checking (2) device control unit (dcu) the dcu manages the following usb upper-layer protocols (ad- dress/endpoint and control-transfer sequence): ?tatus control for each endpoint ?ontrol-transfer sequence control ?emory interface status control (3) memory interface (mif) the mif controls the flow of data transfer between the sie and the multi-channel ram under the management of the dcu. (4) cpu interface (cif) the cif performs the following functions: ?ode setting via registers, dcu control signal generation, dcu status signal reading ?nterrupt signal generation ?nternal bus interface control.
27 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group usb port external circuit configuration the operation mode of the usb port driver circuit can be config- ured by usb control register (address 0010 16 ). figure 25 shows the usb port external circuit block diagram. fig. 25 usb port external circuit (d0+, d0-, usbv ref , tron) block diagram 1 0 u s b r e f e r e n c e v o l t a g e c i r c u i t p l l u c l k c o n v refe v refcon d v c c f u ll speed + - usbe u s b e usb module x out f vco troncon trone usbvref tron d 0 + d0- 2 . 2 f 27 ? u s b e v r e f c o n 01 h i zhiz 3 . 3 v o u t p u t n o r m a l m o d e v r e f e 0 1 u s b v r e f s t a t u s f usb usbdife f u ll speed 3 . 3 v o u t p u t l o w - p o w e r m o d e 0 . 1 f 27 ? 1 . 5 k ?
28 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group endpoint buffer area setting the buffer area used in data transfer can be assigned to any area of the multi-channel ram for each endpoint. buffer area beginning address the buffer area configuration register (address 0fed 16 ) defines the beginning address of the buffer area (every 32 bytes) for each endpoint. however, the only ram area is configurable. 00h [address 0000 16 ], 01h [address 0020 16 ]: not configurable 02h [address 0040 16 ] to 1fh [address 03e0 16 ]: configurable interrupt-source dependant buffer area offset address an offset value is added to the beginning address of each source, which is specified by the interrupt source register (address 001d 16 ), for each endpoint. this section describes in detail the beginning address specified by the buffer area set register as offset address 00h, according to each endpoint. (1) endpoint 00 endpoint 00 has two kinds of interrupt sources for accessing the buffer. the respective address offsets are: bsrdy00 (setup buffer ready interrupt): offset address = 00h brdy00 (out or in buffer ready interrupt): offset address = 08h (2) endpoint 01 the buffer area offset address for each interrupt source for of end- point 01 varies according to the contents of the ep01 set register (address 0019 16 ). in single buffer mode (dblb01 = 0 ): endpoint 01 has only one interrupt source for accessing the buffer. b0rdy01 (buffer 0 ready interrupt): offset address = 00h in double buffer mode (dblb01 = 1 ): endpoint 01 has two kinds of interrupt sources for accessing the buffer. b0rdy01 (buffer 0 ready interrupt): offset address = 00h b1rdy01 (buffer 1 ready interrupt): the offset address varies according to the double buffer begin- ning address set bit (bsiz01). -offset address = 08h when bsiz01 = 00 -offset address = 10h when bsiz01 = 01 -offset address = 40h when bsiz01 = 10 -offset address = 80h when bsiz01 = 11 (3) endpoints 02 and 03 same as endpoint 01. (4) endpoint 10 same as endpoint 00. (5) endpoint 11 endpoint 11 has only one interrupt source for accessing the buffer. b0rdy11 (buffer 0 ready interrupt): offset address = 00h notes the selected ram area must be within addresses 0040 16 to 03ff 16 . make sure the buffer area beginning address is set in agreement with the offset address and the number of transmit/receive data bytes. this is particularly important when in the double buffer mode or when handling 64-byte data. fig. 26 example setting of buffer area beginning address fig. 27 examples of interrupt source dependant buffer area offset address 0fed 16 = 15h 0000 16 0020 16 0040 16 0060 16 02a0 16 03e0 16 memory sfr ram 00 01 02 03 15 1f 0fed 16 disabled to be used 0000 0000 0010 1010 (a) when selecting endpoint 00 memory 02a0 16 02a8 16 offset 00 h 08 h bsrdy00 brdy00 02a0 16 00 h b0rdy01 (d) when selecting endpoint 11 02a0 16 00 h b0rdy11 02a0 16 0320 16 00 h 80 h b0rdy01 b1rdy01 memory offset (b) when selecting single buffer mode memory offset (c) when selecting double buffer mode (when bsiz01 = 11) memory offset
29 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group usb interrupt function usb interrupt control circuit (usbintcon) has 3 requests and 22 usb-device interrupt request sources. each interrupt source register enables the user to easily determine which interrupt has occurred. table 7 shows the list of usb interrupt sources. table 7 usb interrupt sources interrupt request bit (ireq1: address 003c 16 ) usb bus reset usb interrupt bit (usbireq: address 0017 16 ) interrupt source at usb bus reset signal detection: after enabling the usb module (usbe = 1 ), an interrupt request occurs when 2.5 s se0 state is detected in d0+/d0- port. (equivalent to 120-clock length when f usb = 48 mhz) at sof packet receive: after enabling the usb module (usbe = 1 ), an interrupt request occurs when sof packet is detected in d0+/d0- port. its occurrence does not depend on frame-time or crc value after sof packet is transferred. (normally, sof packet detection occurs only when f usb = 48 mhz) at endpoint 00 data transfer complete: buffer ready (read/write enabled state) control transfer completed status stage transition setup buffer ready (read enabled state) control transfer error at endpoint 01 data transfer complete: buffer 0 ready (read/write enabled state) buffer 1 ready (read/write enabled state) transfer error at endpoint 02 data transfer complete: buffer 0 ready (read/write enabled state) buffer 1 ready (read/write enabled state) transfer error at endpoint 03 data transfer complete: buffer 0 ready (read/write enabled state) buffer 1 ready (read/write enabled state) transfer error at endpoint 10 data transfer complete: buffer ready (read/write enabled state) control transfer completed status stage transition setup buffer ready (read enabled state) control transfer error at endpoin 11 data transfer complete: buffer 0 ready (write enabled state) at suspend signal detection: after enabling the usb module (usbe = 1 ), an interrupt request occurs when 3 ms j state is detected in d0+/d0- port. (equivalent to 144,000 clock-length when f usb = 48mhz) at resume signal detection: after enabling the usb module (usbe = 1 ) and resume interrupt (rsme = 1 ), an interrupt request occurs when a bus state change (j state to se0 or k state) is detected in d0- port. usb sof usb device ep00 ep01 ep02 ep03 ep10 ep11 sus rsm
30 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group [epxxreg5] [ep00req] brdy00 ep00 [usbireq] ep00e [usbicon] [ep01req] b0rdy01 ep01 ep01e usb device interrupt request [ep02req] ep02 ep02e [ep03req] ep03 ep03e [ep10req] ep10 ep10e [ep11req] b0rdy11 ep11 ep11e sus suse rsm rsme ctend00 ctsts00 bsydy00 err00 b1rdy01 err01 b0rdy02 b1rdy02 err02 b0rdy03 b1rdy03 err03 brdy10 ctend10 ctsts10 bsydy10 err10 fig. 28 usb device interrupt control
31 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group usb register list the usb register list is shown below. fig. 29 usb related registers 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0fec 16 0fed 16 usb control register usb function/hub enable register usb function address register usb hub address register frame number register low frame number register high usb interrupt source enable register usb interrupt source register endpoint index register endpoint field register 1 endpoint field register 2 endpoint field register 3 endpoint field register 4 endpoint field register 5 endpoint field register 6 endpoint field register 7 endpoint field register 8 endpoint field register 9 usbcon usbae usba0 usba1 fnuml fnumh usbicon usbireq usbindex epxxreg1 epxxreg2 epxxreg3 epxxreg4 epxxreg5 epxxreg6 epxxreg7 epxxreg8 epxxreg9 usbe uclkcon usbdife vrefe vrefcon trone troncon wkup symbol address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ad1e ad0e usbadd0[6:0] usbadd1[6:0] fnum[7:0] fnum[10:8] rsme suse ep11e ep10e ep03e ep02e ep01e ep00e rsm sus ep11 ep10 ep03 ep02 ep01 ep00 adidx 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0fec 16 0fed 16 (1) endpoint 00 (2) endpoint 01 (3) endpoint 02 (4) endpoint 03 (5) endpoint 10 (6) endpoint 11 ep00stg ep00con1 ep00con2 ep00con3 ep00req ep00byt ep00buf setup00 ep00 stage register ep00 control register 1 ep00 control register 2 ep00 control register 3 ep00 interrupt source register ep00 transmit/receive byte number register ep00 buffer area set register bval00 ctende00 err00 bsrdy00 ctsts00 ctend00 brdy00 bbyt00[3:0] 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0fec 16 0fed 16 ep01 set register ep01 control register 1 ep01 control register 2 ep01 control register 3 ep01 interrupt source register ep01 byte number register 0 ep01 byte number register 1 ep01 max. packet size register ep01 buffer area set register ep01cfg ep01con1 ep01con2 ep01con3 ep01req ep01byt0 ep01byt1 ep01max ep01buf typ01[1:0] dir01 itmd01 sqcl01 dblb01 bsiz01[1:0] b0val01 b1val01 err01 b1rdy01 b0rdy01 b0byt01[6:0] b1byt01[6:0] mxps01[6:0] 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0fec 16 0fed 16 ep02cfg ep02con1 ep02con2 ep02con3 ep02req ep02byt0 ep02byt1 ep02max ep02buf typ02[1:0] dir02 itmd02 sqcl02 dblb02 bsiz02[1:0] b0val02 b1val02 err02 b1rdy02 b0rdy02 b0byt02[6:0] b1byt02[6:0] mxps02[6:0] 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0fec 16 0fed 16 ep03 set register ep03 control register 1 ep03 control register 2 ep03 control register 3 ep03 interrupt source register ep03 byte number register 0 ep03 byte number register 1 ep03 max. packet size register ep03 buffer area set register ep02 set register ep02 control register 1 ep02 control register 2 ep02 control register 3 ep02 interrupt source register ep02 byte number register 0 ep02 byte number register 1 ep02 max. packet size register ep02 buffer area set register ep03cfg ep03con1 ep03con2 ep03con3 ep03req ep03byt0 ep03byt1 ep03max ep03buf typ03[1:0] dir03 dir11 itmd03 sqcl03 dblb03 bsiz03[1:0] b0val03 b1val03 err03 b1rdy03 b0rdy03 b0byt03[6:0] b1byt03[6:0] mxps03[6:0] 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0fec 16 0fed 16 ep10 set register ep10 control register 1 ep10 control register 2 ep10 control register 3 ep10 interrupt source register ep10 transmit/receive byte number register ep10 buffer area set register ep10stg ep10con1 ep10con2 ep10con3 ep10req ep10byt ep10buf setup10 bval10 ctende10 err10 bsrdy10 ctsts10 ctend10 brdy10 bbyt10[3:0] 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0fec 16 0fed 16 ep11 set register ep11 control register 1 ep11 control register 2 ep11 interrupt source register ep11 transmit byte number register ep11 buffer area set register ep11cfg ep11con1 ep11con2 ep11req ep11byt0 ep11buf typ11 sqcl11 b0val11 b0rdy11 b0byt11 pid11[1:0] badd11[4:0] : not used usb sfr pid00[1:0] badd02[4:0] badd01[4:0] pid01[1:0] pid02[1:0] badd03[4:0] badd10[4:0] pid03[1:0] pid10[1:0] epidx[1:0] badd00[4:0]
32 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group usb related registers the usb related registers are shown below. fig. 30 structure of usb control register fig. 31 structure of usb function/hub enable register b7 at reset w function bit name bit symbol b0 remote wakeup bit tron output control bit tron output enable bit usb reference voltage control bit usb reference voltage enable bit usb difference input enable bit usb clock select bit usb module operation enable bit wkup troncon trone vrefcon vrefe usbdife uclkcon usbe o o o o o o o o o o o o o o o o 0 0 0 0 0 0 0 0 usb control register ( usbcon) [address 0010 16 ] : state remaining 0 : returning to bus idle state by writing 1 first and then 0 . (remote wakeup signal) 1 : k-state output 0 : l output mode (valid in trone = 1 ) 1 : h output mode (valid in trone = 1 ) 0 : tron port output disabled (hi-z state) 1 : tron port output enabled 0 : normal mode (valid in vrefe = 1 ) 1 : low current mode (valid in vrefe = 1 ) 0 : usb reference voltage circuit operation disabled 1 : usb reference voltage circuit operation enabled 0 : upstream-port difference input circuit operation disabled 1 : upstream--port difference input circuit operation enabled 0 : external oscillating clock f(x in ) 1 : pll circuit output clock (f vco ) 0 : usb module reset 1 : usb module operation enabled h/w s/w r b7 bit name bit symbol b0 usb function enable bit usb hub enable bit not used ad0e ad1e b7:b2 0 0 usb function/hub enable register (usbae) [address 0011 16 ] 0: usb function address register invalidated 1: usb function address register validated 0: usb hub address register invalidated 1: usb hub address register validated write 0 when writing. 0 is read when reading. at reset function h/w s/w o o o o o o : state remaining 000000 w r
33 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group fig. 32 structure of usb function address register fig. 33 structure of usb hub address register fig. 34 structure of frame number register low fig. 35 structure of frame number register high b7 b0 usb function address bit not used usbadd0 [6:0] b7 0 0 usb function address register ( usba0) [address 0012 16 ] bit name bit symbol at reset function h/w s/w o o o o : state remaining in ad0e = 0 , this value changes after writing. in ad0e = 1 , this value changes after completion of set_address control transferring. write 0 when writing. 0 is read when reading. 0 w r b7 b0 usb hub address bit not used usbadd1 [6:0] b7 0 0 usb hub address register ( usba1) [address 0013 16 ] bit name bit symbol at reset function h/w s/w o o o o : state remaining in ad1e = 0 , this value changes after writing. in ad1e = 1 , this value changes after completion of set_address control transferring. write 0 when writing. 0 is read when reading. 0 w r b7 b0 frame number low bit fnum [7:0] in- definite in- definite frame number register low ( fnuml) [address 0014 16 ] the frame number is updated at sof reception. bit name bit symbol at reset function h/w s/w o ? w r b7 b0 fnum [10:8] b7:b3 frame number register high ( fnumh) [address 0015 16 ] in- definite in- definite bit name bit symbol at reset function h/w s/w o o frame number high bit not used the frame number is updated at sof reception. write 0 when writing. 0 is read when reading. ? o : state remaining 00000 w r
34 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group fig. 36 structure of usb interrupt source enable register b7 b0 ep00e ep01e ep02e ep03e ep10e ep11e suse rsme 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 usb interrupt source enable register ( usbicon) [address 0016 16 ] 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled bit name bit symbol at reset function h/w s/w o o o o o o o o o o o o o o o o usb function/endpoint 0 interrupt enable bit usb function/endpoint 1 interrupt enable bit usb function/endpoint 2 interrupt enable bit usb function/endpoint 3 interrupt enable bit usb hub/endpoint 0 interrupt enable bit usb hub/endpoint 1 interrupt enable bit suspend interrupt enable bit resume interrupt enable bit w r
35 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group fig.37 structure of usb interrupt source register b7 b0 usb function/endpoint 0 interrupt bit usb function/endpoint 1 interrupt bit usb function/endpoint 2 interrupt bit usb function/endpoint 3 interrupt bit usb hub/endpoint 0 interrupt bit usb hub/endpoint 1 interrupt bit suspend interrupt bit resume interrupt bit ep00 ep01 ep02 ep03 ep10 ep11 sus rsm 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 usb interrupt source register ( usbireq) [address 0017 16 ] bit name bit symbol at reset function h/w s/w o o o o o o o o ? ? ? ? ? ? o ? this bit is set to 1 when any one of ep00 interrupt source register s bits at least is set to 1 . this bit is cleared to 0 by clearing ep00 interrupt source register to 00 16 . writing to this bit causes no state change. this bit is set to 1 when any one of ep01 interrupt source register s bits at least is set to 1 . this bit is cleared to 0 by clearing ep01 interrupt source register to 00 16 . writing to this bit causes no state change. this bit is set to 1 when any one of ep02 interrupt source register s bits at least is set to 1 . this bit is cleared to 0 by clearing ep02 interrupt source register to 00 16 . writing to this bit causes no state change. this bit is set to 1 when any one of ep03 interrupt source register s bits at least is set to 1 . this bit is cleared to 0 by clearing ep03 interrupt source register to 00 16 . writing to this bit causes no state change. this bit is set to 1 when any one of ep10 interrupt source register s bits at least is set to 1 . this bit is cleared to 0 by clearing ep10 interrupt source register to 00 16 . writing to this bit causes no state change. this bit is set to 1 when any one of ep11 interrupt source register s bits at least is set to 1 . this bit is cleared to 0 by clearing ep11 interrupt source register to 00 16 . writing to this bit causes no state change. 0 : no interrupt request issued 1 : interrupt request issued this bit is set to 1 when detecting 3 ms or more of j- state, using usb clock (f usb ) at 48 mhz. 0 can be set by software, but 1 cannot be set. this bit is set to 1 when the usb bus state changes from j-state to k-state or se0 in the resume interrupt enable bit = 1 . it is also 1 in the condition of internal clock stopped. this bit is cleared to 0 by clearing the resume interrupt enable bit. writing to this bit causes no state change. w r
36 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group fig. 38 structure of endpoint index register b7 b0 endpoint index bit address index bit not used epidx [1:0] adidx b7:b3 0 0 endpoint index register ( usbindex) [address 0018 16 ] b1 b0 0 0 : endpoint 0 0 1 : endpoint 1 1 0 : endpoint 2 1 1 : endpoint 3 0 : usb function 1 : usb hub write 0 when writing. 0 is read when reading. bit name bit symbol at reset function o o o o o o : state remaining h/w s/w 00000 w r
37 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group (1) endpoint 00 fig. 39 structure of ep00 stage register fig. 40 structure of ep00 control register 1 fig. 41 structure of ep00 control register 2 b7 b0 setup packet detection bit not used setup00 b7:b1 1 1 ep00 stage register ( ep00stg) [address 0019 16 ] bit name bit symbol at reset function h/w s/w this bit is set to 1 at reception of setup packet. writing 0 to this bit clears this bit if the next setup token does not occur. writing 1 to this bit causes no state change of the status flags. write 0 when writing. 0 is read when reading. o o o o : state remaining 000 0 000 w r b7 b0 response pid bit not used pid00 [1:0] b7:b2 0 ep00 control register 1 ( ep00con1) [address 001a 16 ] bit name bit symbol at reset function h/w s/w b1 b0 0 0 : nak 0 1 : automatic response (ack, nak, data0, data1) 1 x : stall at occurrence of control transfer error: b1 is set to 1 by the hardware. at reception of setup token: b1 and b0 are cleared to 0 by the hardware. write 0 when writing. 0 is read when reading. o o o o : state remaining 000000 w r b7 b0 buffer enable bit not used bval00 b7:b1 0 ep00 control register 2 ( ep00con2) [address 001b 16 ] bit name bit symbol at reset function h/w s/w 0 : nak transmission (sie is disabled to read a buffer.) 1 : transmitting/receiving data set state (sie is possible to read from/write to a buffer.) at reception of setup token: this bit is cleared to 0 by the hardware. write 0 when writing. 0 is read when reading. o o o o : state remaining 000 0 0 0 0 w r
38 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group fig. 42 structure of ep00 control register 3 fig. 43 structure of ep00 interrupt source register b7 b0 control transfer completion enable bit not used ctende00 b7:b1 0 ep00 control register 3 ( ep00con3) [address 001c 16 ] 0 : nak transmission in the status stage 1 : control transfer completion enabled (sie transmits null/ack.) (valid in pid00 = 01 2 ) at reception of setup token: this bit is cleared to 0 by the hardware. write 0 when writing. 0 is read when reading. o o o o : state remaining bit name bit symbol at reset function h/w s/w 000 0 0 0 0 w r b7 b0 usb function/endpoint 0 buffer ready interrupt bit usb function/endpoint 0 control transfer completion interrupt bit usb function/endpoint 0 status stage transition interrupt bit usb function/endpoint 0 setup buffer ready interrupt bit usb function/endpoint 0 error interrupt bit not used brdy00 ctend00 ctsts00 bsrdy00 err00 b7:b5 0 0 0 0 0 0 0 0 0 0 ep00 interrupt source register (ep00req) [address 001d 16 ] bit name bit symbol at reset function h/w s/w o o o o o o o o o o o o 0: no interrupt request issued 1: interrupt request issued this bit is set to 1 when the buffer is ready state (enabled to be read/written) on usb function/endpoint 0. 0 can be set by software, but 1 cannot be set. 0: no interrupt request issued 1: interrupt request issued this bit is set to 1 when control transfer is completed (null/ack transmission in the status stage) on usb function/endpoint 0. 0 can be set by software, but 1 cannot be set. 0: no interrupt request issued 1: interrupt request issued this bit is set to 1 when transition to status stage occurs in ctende00 = 0 (control transfer completion disabled) on usb function/endpoint 0. 0 can be set by software, but 1 cannot be set. at transfer of control write: when receiving in-token in data stage (out) at transfer of control read: when receiving out-token in data stage (in) at no data transfer: nothing occurs. 0: no interrupt request issued 1: interrupt request issued this bit is set to 1 when the exclusive buffer for setup is ready state (enabled to be read) on usb function/endpoint 0. 0 can be set by software, but 1 cannot be set. 0: no interrupt request issued 1: interrupt request issued this bit is set to 1 when control transfer error occurs on usb function/endpoint 0. this bit is cleared to 0 by the hardware when receiving setup token. 0 can be set by software, but 1 cannot be set. write 0 when writing. 0 is read when reading. : state remaining 000 w r
39 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group fig. 44 structure of ep00 transmit/receive byte number register fig. 45 structure of ep00 buffer area set register b7 b0 bbyt00 [3:0] b7:b4 0 ep00 transmit/receive byte number register ( ep00byt) [address 001e 16 ] out : the received byte number is automatically set. in : set the transmitting byte number. write 0 when writing. 0 is read when reading. bit name bit symbol at reset function h/w s/w o o o o transmit/receive byte number bit not used : state remaining 0000 w r b7 b0 ep00 beginning address set bit not used badd00 [4:0] b7:b5 0 ep00 buffer area set register ( ep00buf) [address 0fed 16 ] bit name bit symbol at reset function h/w s/w set the beginning address of ep00 s buffer area. (32-byte unit) b4b3b2b1b0 0 0 0 1 0 : 0040 16 0 0 0 1 1 : 0060 16 .............. 1 1 1 1 0 : 03c0 16 1 1 1 1 1 : 03e0 16 write 0 when writing. 0 is read when reading. o o o o : state remaining 000 w r
40 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group (2) endpoint 01 fig. 46 structure of ep01 set register fig. 47 structure of ep01 control register 1 b7 b0 double buffer beginning address set bit buffer mode select bit sequence toggle bit clear bit interrupt toggle mode select bit transfer direction bit transfer type bite bsiz01 [1:0] dblb01 sqcl01 itmd01 dir01 typ01 [1:0] 0 0 0 0 0 0 ep01 set register ( ep01cfg) [address 0019 16 ] bit name bit symbol at reset function h/w s/w in double buffer mode set the beginning address of buffer 1 area, using a relative value for the beginning address of buffer 0. b1b0 0 0 = 8 bytes 0 1 = 16 bytes 1 0 = 64 bytes 1 1 = 128 bytes 0 : single buffer mode 1 : double buffer mode 0 : toggle bit clear disabled 1 : writing 1 clears the toggle bit and data0 is used as the next data pid. 0 is always read when reading. 0 : normal mode 1 : contin uous toggle mode (valid at interrupt in transfer) 0 : out (data is received from the host.) 1 : in (data is transmitted to the host.) b7b6 0 0 : transfer disabled 0 1 : bulk transfer 1 0 : interrupt transfer 1 1 : isochronous transfer o o o o o o o o o o o o : state remaining w r b7 b0 response pid bit not used pid01 [1:0] b7:b2 0 ep01 control register 1 ( ep01con1) [address 001a 16 ] bit name bit symbol at reset function h/w s/w b1 b0 0 0 : nak 0 1 : automatic response (ack, nak, data0, data1) 1 x : stall at occurrence of over-max. packet size : b1 is set to 1 by the hardware. write 0 when writing. 0 is read when reading. o o o o : state remaining 000000 w r
41 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group fig. 49 structure of ep01 control register 3 fig. 50 structure of ep01 interrupt source register fig. 48 structure of ep01 control register 2 b7 b0 b0val01 b7:b1 0 ep01 control register 2 ( ep01con2) [address 001b 16 ] bit name bit symbol at reset function h/w s/w o o o o : state remaining buffer 0 enable bit not used when the selected endpoint is in, writing 1 to this bit makes the transmitting data a set state (sie is possible to read). when the selected endpoint is out, writing 1 to this bit makes data reception possible (sie is possible to write). write 0 when writing. 0 is read when reading. 00 0 00 0 0 w r b7 b0 b1val01 b7:b1 0 ep01 control register 3 ( ep01con3) [address 001c 16 ] bit name bit symbol at reset function h/w s/w o o o o : state remaining buffer 1 enable bit not used when the selected endpoint is in, writing 1 to this bit makes the transmitting data a set state (sie is possible to read). when the selected endpoint is out, writing 1 to this bit makes data reception possible (sie is possible to write). in double buffer mode this bit is valid. write 0 when writing. 0 is read when reading. 0000000 w r b7 b0 b0rdy01 b1rdy01 err01 b7:b3 0 0 0 0 0 0 ep01 interrupt source register (ep01req) [address 001d 16 ] bit name bit symbol at reset function h/w s/w o o o o o o o o usb function/endpoint 1 buffer 0 ready interrupt bit usb function/endpoint 1 buffer 1 ready interrupt bit usb function/endpoint 1 error interrupt bit not used 0: no interrupt request issued 1: interrupt request issued this bit is set to 1 when the buffer 0 is ready state (enabled to be read/written) on usb function/endpoint 1. 0 can be set by software, but 1 cannot be set. 0: no interrupt request issued 1: interrupt request issued in single buffer mode this bit is invalid. this bit is set to 1 when the buffer 1 is ready state (enabled to be read/written) on usb function/endpoint 1 in double buffer mode. 0 can be set by software, but 1 cannot be set. 0: no interrupt request issued 1: interrupt request issued this bit is set to 1 when stall response occurs on usb function/endpoint 1. 0 can be set by software, but 1 cannot be set. write 0 when writing. 0 is read when reading. 00000 w r
42 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group fig. 51 structure of ep01 byte number register 0 fig. 52 structure of ep01 byte number register 1 fig. 53 structure of ep01 max. packet size register b7 b0 b0byt01 [6:0] b7 0 0 ep01 byte number register 0 ( ep01byt0) [address 001e 16 ] bit name bit symbol at reset function h/w s/w in : transmit byte number bit out : receive byte number bit not used : state remaining single buffer mode: set the transmitting byte number. double buffer mode : set the transmitting byte number of buffer 0. single buffer mode : the received byte number is automatically set. double buffer mode : the received byte number of buffer 0 is automatically set. write 0 when writing. 0 is read when reading. o o o o ? o 0 w r b7 b0 b1byt01 [6:0] b7 0 0 ep01 byte number register 1 ( ep01byt1) [address 001f 16 ] bit name bit symbol at reset function h/w s/w in : transmit byte number bit out : receive byte number bit not used : state remaining single buffer mode: these bits are invalid. double buffer mode : set the transmitting byte number of buffer 1. single buffer mode: these bits are invalid. double buffer mode : the received byte number of buffer 1 is automatically set. write 0 when writing. 0 is read when reading. o o o o ? o 0 w r b7 b0 mxps01 [6:0] b7 ep01 max. packet size register (ep01max) [address 0fec 16 ] 0 bit name bit symbol at reset function h/w s/w : state remaining o o o o max. packet size bit not used in : these bits are invalid. out : set the maximum packet size. write 0 when writing. 0 is read when reading. 0 w r
43 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group fig. 54 structure of ep01 buffer area set register b7 b0 ep01 beginning address set bit not used badd01 [4:0] b7:b5 0 ep01 buffer area set register ( ep01buf) [address 0fed 16 ] bit name bit symbol at reset function h/w s/w set the beginning address of ep01 s buffer area. (32-byte unit) b4b3b2b1b0 0 0 0 1 0 : 0040 16 0 0 0 1 1 : 0060 16 .............. 1 1 1 1 0 : 03c0 16 1 1 1 1 1 : 03e0 16 write 0 when writing. 0 is read when reading. o o o o : state remaining 000 w r
44 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group (3) endpoint 02 fig. 55 structure of ep02 set register fig. 56 structure of ep02 control register 1 b7 b0 double buffer beginning address set bit buffer mode select bit sequence toggle bit clear bit interrupt toggle mode select bit transfer direction bit transfer type bite bsiz02 [1:0] dblb02 sqcl02 itmd02 dir02 typ02 [1:0] 0 0 0 0 0 0 ep02 set register ( ep02cfg) [address 0019 16 ] bit name bit symbol at reset function h/w s/w in double buffer mode set the beginning address of buffer 1 area, using a relative value for the beginning address of buffer 0. b1b0 0 0 = 8 bytes 0 1 = 16 bytes 1 0 = 64 bytes 1 1 = 128 bytes 0 : single buffer mode 1 : double buffer mode 0 : toggle bit clear disabled 1 : writing 1 clears the toggle bit and data0 is used as the next data pid. 0 is always read when reading. 0 : normal mode 1 : contin uous toggle mode (valid at interrupt in transfer) 0 : out (data is received from the host.) 1 : in (data is transmitted to the host.) b7b6 0 0 : transfer disabled 0 1 : bulk transfer 1 0 : interrupt transfer 1 1 : isochronous transfer o o o o o o o o o o o o : state remaining w r b7 b0 response pid bit not used pid02 [1: 0] b7:b2 0 ep02 control register 1 ( ep02con1) [address 001a 16 ] bit name bit symbol at reset function h/w s/w b1 b0 0 0 : nak 0 1 : automatic response (ack, nak, data0, data1) 1 x : stall at occurrence of over-max. packet size : b1 is set to 1 by the hardware. write 0 when writing. 0 is read when reading. o o o o : state remaining 00 0 0 00 w r
45 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group fig. 57 structure of ep02 control register 2 fig. 58 structure of ep02 control register 3 fig. 59 structure of ep02 interrupt source register b7 b0 b0val02 b7:b1 0 ep02 control register 2 ( ep02con2) [address 001b 16 ] bit name bit symbol at reset function h/w s/w o o o o : state remaining buffer 0 enable bit not used when the selected endpoint is in, writing 1 to this bit makes the transmitting data a set state (sie is possible to read). when the selected endpoint is out, writing 1 to this bit makes data reception possible (sie is possible to write). write 0 when writing. 0 is read when reading. 00 0 00 0 0 w r b7 b0 b1val02 b7:b1 0 ep02 control register 3 ( ep02con3) [address 001c 16 ] bit name bit symbol at reset function h/w s/w o o o o : state remaining buffer 1 enable bit not used when the selected endpoint is in, writing 1 to this bit makes the transmitting data a set state (sie is possible to read). when the selected endpoint is out, writing 1 to this bit makes data reception possible (sie is possible to write). in double buffer mode this bit is valid. write 0 when writing. 0 is read when reading. 00 0 00 0 0 w r b7 b0 b0rdy02 b1rdy02 err02 b7 to b3 0 0 0 0 0 0 ep02 interrupt source register (ep02req) [address 001d 16 ] bit name bit symbol at reset function h/w s/w o o o o o o o o usb function/endpoint 2 buffer 0 ready interrupt bit usb function/endpoint 2 buffer 1 ready interrupt bit usb function/endpoint 2 error interrupt bit not used 0 : no interrupt request issued 1 : interrupt request issued this bit is set to 1 when the buffer 0 is ready state (enabled to be read/written) on usb function/endpoint 2. 0 can be set by software, but 1 cannot be set. 0 : no interrupt request issued 1 : interrupt request issued in single buffer mode this bit is invalid. this bit is set to 1 when the buffer 1 is ready state (enabled to be read/written) on usb function/endpoint 2 in double buffer mode. 0 can be set by software, but 1 cannot be set. 0 : no interrupt request issued 1 : interrupt request issued this bit is set to 1 when stall response occurs on usb function/endpoint 2. 0 can be set by software, but 1 cannot be set. write 0 when writing. 0 is read when reading. 00 0 00 w r
46 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group fig. 60 structure of ep02 byte number register 0 fig. 61 structure of ep02 byte number register 1 fig. 62 structure of ep02 max. packet size register b7 b0 b0byt02 [6:0] b7 0 0 ep02 byte number register 0 ( ep02byt0) [address 001e 16 ] bit name bit symbol at reset function h/w s/w in : transmit byte number bit out : receive byte number bit not used : state remaining single buffer mode: set the transmitting byte number. double buffer mode : set the transmitting byte number of buffer 0. single buffer mode: the received byte number is automatically set. double buffer mode : the received byte number of buffer 0 is automatically set. write 0 when writing. 0 is read when reading. o o o o ? o 0 w r b7 b0 b1byt02 [6:0] b7 0 0 ep02 byte number register 1 ( ep02byt1) [address 001f 16 ] bit name bit symbol at reset function h/w s/w in : transmit byte number bit out : receive byte number bit not used : state remaining single buffer mode: these bits are invalid. double buffer mode : set the transmitting byte number of buffer 1. single buffer mode: these bits are invalid. double buffer mode : the received byte number of buffer 1 is automatically set. write 0 when writing. 0 is read when reading. o o o o ? o 0 w r b7 b0 mxps02 [6:0] b7 ep02 max. packet size register (ep02max) [address 0fec 16 ] 0 bit name bit symbol at reset function h/w s/w : state remaining o o o o max. packet size bit not used in : these bits are invalid. out : set the maximum packet size. write 0 when writing. 0 is read when reading. 0 w r
47 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group fig. 63 structure of ep02 buffer area set register b7 b0 ep02 beginning address set bit not used badd02 [4:0] b7:b5 0 ep02 buffer area set register ( ep02buf) [address 0fed 16 ] bit name bit symbol at reset function h/w s/w set the beginning address of ep02 s buffer area. (32-byte unit) b4b3b2b1b0 0 0 0 1 0 : 0040 16 0 0 0 1 1 : 0060 16 .............. 1 1 1 1 0 : 03c0 16 1 1 1 1 1 : 03e0 16 write 0 when writing. 0 is read when reading. o o o o : state remaining 000 w r
48 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group (4) endpoint 03 fig. 64 structure of ep03 set register fig. 65 structure of ep03 control register 1 b7 b0 double buffer beginning address set bit buffer mode select bit sequence toggle bit clear bit interrupt toggle mode select bit transfer direction bit transfer type bit bsiz03 [1:0] dblb03 sqcl03 itmd03 dir03 typ03 [1:0] 0 0 0 0 0 0 ep03 set register ( ep03cfg) [address 0019 16 ] bit name bit symbol at reset function h/w s/w in double buffer mode set the beginning address of buffer 1 area, using a relative value for the beginning address of buffer 0. b1b0 0 0 = 8 bytes 0 1 = 16 bytes 1 0 = 64 bytes 1 1 = 128 bytes 0 : single buffer mode 1 : double buffer mode 0 : toggle bit clear disabled 1 : writing 1 clears the toggle bit and data0 is used as the next data pid. 0 is always read when reading. 0 : normal mode 1 : contin uous toggle mode (valid at interrupt in transfer) 0 : out (data is received from the host.) 1 : in (data is transmitted to the host.) b7b6 0 0 : transfer disabled 0 1 : bulk transfer 1 0 : interrupt transfer 1 1 : isochronous transfer o o o o o o o o o o o o : state remaining w r b7 b0 response pid bit not used pid03 [1:0] b7:b2 0 ep03 control register 1 ( ep03con1) [address 001a 16 ] bit name bit symbol at reset function h/w s/w b1 b0 0 0 : nak 0 1 : automatic response (ack, nak, data0, data1) 1 x : stall at occurrence of over-max. packet size : b1 is set to 1 by the hardware. write 0 when writing. 0 is read when reading. o o o o : state remaining 000000 w r
49 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group fig. 66 structure of ep03 control register 2 fig. 67 structure of ep03 control register 3 fig. 68 structure of ep03 interrupt source register b7 b0 b0val03 b7:b1 0 ep03 control register 2 ( ep03con2) [address 001b 16 ] bit name bit symbol at reset function h/w s/w o o o o : state remaining buffer 0 enable bit not used when the selected endpoint is in, writing 1 to this bit makes the transmitting data a set state (sie is possible to read). when the selected endpoint is out, writing 1 to this bit makes data reception possible (sie is possible to write). write 0 when writing. 0 is read when reading. 00 0 00 0 0 w r b7 b0 b1val03 b7:b1 0 ep03 control register 3 ( ep03con3) [address 001c 16 ] bit name bit symbol at reset function h/w s/w o o o o : state remaining buffer 1 enable bit not used when the selected endpoint is in, writing 1 to this bit makes the transmitting data a set state (sie is possible to read). when the selected endpoint is out, writing 1 to this bit makes data reception possible (sie is possible to write). in double buffer mode this bit is valid. write 0 when writing. 0 is read when reading. 0000000 w r b7 b0 b0rdy03 b1rdy03 err03 b7:b3 0 0 0 0 0 0 ep03 interrupt source register (ep03req) [address 001d 16 ] bit name bit symbol at reset function h/w s/w o o o o o o o o usb function/endpoint 3 buffer 0 ready interrupt bit usb function/endpoint 3 buffer 1 ready interrupt bit usb function/endpoint 3 error interrupt bit not used 0 : no interrupt request issued 1 : interrupt request issued this bit is set to 1 when the buffer 0 is ready state (enabled to be read/written) on usb function/endpoint 3. 0 can be set by software, but 1 cannot be set. 0 : no interrupt request issued 1 : interrupt request issued in single buffer mode this bit is invalid. this bit is set to 1 when the buffer 1 is ready state (enabled to be read/written) on usb function/endpoint 3 in double buffer mode. 0 can be set by software, but 1 cannot be set. 0 : no interrupt request issued 1 : interrupt request issued this bit is set to 1 when stall response occurs on usb function/endpoint 3. 0 can be set by software, but 1 cannot be set. write 0 when writing. 0 is read when reading. 00000 w r
50 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group fig. 69 structure of ep03 byte number register 0 fig. 71 structure of ep03 max. packet size register fig. 70 structure of ep03 byte number register 1 b7 b0 b0byt03 [6:0] b7 0 0 ep03 byte number register 0 ( ep03byt0) [address 001e 16 ] bit name bit symbol at reset function h/w s/w in : transmit byte number bit out : receive byte number bit not used : state remaining single buffer mode: set the transmitting byte number. double buffer mode : set the transmitting byte number of buffer 0. single buffer mode: the received byte number is automatically set. double buffer mode : the received byte number of buffer 0 is automatically set. write 0 when writing. 0 is read when reading. o o o o ? o 0 w r b7 b0 b1byt03 [6:0] b7 0 0 ep03 byte number register 1 ( ep03byt1) [address 001f 16 ] bit name bit symbol at reset function h/w s/w in : transmit byte number bit out : receive byte number bit not used : state remaining single buffer mode: these bits are invalid. double buffer mode : set the transmitting byte number of buffer 1. single buffer mode: these bits are invalid. double buffer mode : the received byte number of buffer 1 is automatically set. write 0 when writing. 0 is read when reading. o o o o ? o 0 w r b7 b0 mxps03 [6:0] b7 ep03 max. packet size register (ep03max) [address 0fec 16 ] 0 bit name bit symbol at reset function h/w s/w : state remaining o o o o max. packet size bit not used in : these bits are invalid. out : set the maximum packet size. write 0 when writing. 0 is read when reading. 0 w r
51 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group fig. 72 structure of ep03 buffer area set register b7 b0 ep03 beginning address set bit not used badd03 [4:0] b7:b5 0 ep03 buffer area set register ( ep03buf) [address 0fed 16 ] bit name bit symbol at reset function h/w s/w set the beginning address of ep03 s buffer area. (32-byte unit) b4b3b2b1b0 0 0 0 1 0 : 0040 16 0 0 0 1 1 : 0060 16 .............. 1 1 1 1 0 : 03c0 16 1 1 1 1 1 : 03e0 16 write 0 when writing. 0 is read when reading. o o o o : state remaining 000 w r
52 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group (5) endpoint 10 fig. 73 structure of ep10 stage register fig. 74 structure of ep10 control register 1 fig. 75 structure of ep10 control register 2 b7 b0 setup packet detection bit not used setup10 b7:b1 1 1 ep10 stage register ( ep10stg) [address 0019 16 ] bit name bit symbol at reset function h/w s/w this bit is set to 1 at reception of setup packet. writing 0 clears this bit if the next setup token does not occur. writing 1 causes no state change of the status flags. this bit change is not for an interrupt source. write 0 when writing. 0 is read when reading. o o o o : state remaining 000 0 000 w r b7 b0 response pid bit not used pid10 [1:0] b7:b2 0 ep10 control register 1 ( ep10con1) [address 001a 16 ] bit name bit symbol at reset function h/w s/w b1 b0 0 0 : nak 0 1 : automatic response (ack, nak, data0, data1) 1 x : stall at occurrence of control transfer error: b1 is set to 1 by the hardware. at reception of setup token: b1 and b0 are cleared to 0 by the hardware. write 0 when writing. 0 is read when reading. o o o o : state remaining 000000 w r b7 b0 buffer enable bit not used bval10 b7:b1 0 ep10 control register 2 ( ep10con2) [address 001b 16 ] bit name bit symbol at reset function h/w s/w 0 : nak transmission (sie is disabled to read a buffer.) 1 : transmitting/receiving data set state (sie is possible to read from/write to a buffer.) (valid in pid10 = 01 2 ) at reception of setup token: this bit is cleared to 0 by the hardware. write 0 when writing. 0 is read when reading. o o o o : state remaining 000 0 0 0 0 w r
53 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group fig. 76 structure of ep10 control register 3 fig. 77 structure of ep10 interrupt source register b7 b0 control transfer completion enable bit not used ctende10 b7:b1 0 ep10 control register 3 ( ep10con3) [address 001c 16 ] 0 : nak transmission in the status stage 1 : control transfer completion enabled (sie transmits null/ack.) (valid in pid10 = 01 2 ) at reception of setup token: this bit is cleared to 0 by the hardware. write 0 when writing. 0 is read when reading. o o o o : state remaining bit name bit symbol at reset function h/w s/w 000 0 0 0 0 w r b7 b0 usb hub/endpoint 10 buffer ready interrupt bit usb hub/endpoint 10 control transfer completion interrupt bit usb hub/endpoint 10 status stage transition interrupt bit usb hub/endpoint 10 setup buffer ready interrupt bit usb hub/endpoint 10 error interrupt bit not used brdy10 ctend10 ctsts10 bsrdy10 err10 b7:b5 0 0 0 0 0 0 0 0 0 0 ep10 interrupt source register (ep10req) [address 001d 16 ] bit name bit symbol at reset function h/w s/w o o o o o o o o o o o o 0: no interrupt request issued 1: interrupt request issued this bit is set to 1 when the buffer is ready state (enabled to be read/written) on usb hub/endpoint 10. 0 can be set by software, but 1 cannot be set. 0: no interrupt request issued 1: interrupt request issued this bit is set to 1 when control transfer is completed (null/ack transmission in the status stage) on usb hub/endpoint 10. 0 can be set by software, but 1 cannot be set. 0: no interrupt request issued 1: interrupt request issued this bit is set to 1 when transition to status stage occurs in ctende10 = 0 (control transfer completion disabled) on usb hub/endpoint 10. 0 can be set by software, but 1 cannot be set. at transfer of control write: when receiving in-token in data stage (out) at transfer of control read: when receiving out-token in data stage (in) at no data transfer: nothing occurs. 0: no interrupt request issued 1: interrupt request issued this bit is set to 1 when the exclusive buffer for setup is ready state (enabled to be read) on usb hub/endpoint 10. 0 can be set by software, but 1 cannot be set. 0: no interrupt request issued 1: interrupt request issued this bit is set to 1 when control transfer error occurs on usb hub/endpoint 10. this bit is cleared to 0 by the hardware when receiving setup token. 0 can be set by software, but 1 cannot be set. write 0 when writing. 0 is read when reading. : state remaining 000 w r
54 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group fig. 78 structure of ep10 transmit/receive byte number register fig. 79 structure of ep10 buffer area set register b7 b0 bbyt10 [3:0] b7:b4 0 ep10 transmit/receive byte number register ( ep10byt) [address 001e 16 ] out : the received byte number is automatically set. in : set the transmitting byte number. write 0 when writing. 0 is read when reading. bit name bit symbol at reset function h/w s/w o o o o transmit/receive byte number bit not used : state remaining 0000 w r b7 b0 ep10 beginning address set bit not used badd10 [4:0] b7:b5 0 ep10 buffer area set register ( ep10buf) [address 0fed 16 ] bit name bit symbol at reset function h/w s/w set the beginning address of ep10 s buffer area. (32-byte unit) b4b3b2b1b0 0 0 0 1 0 : 0040 16 0 0 0 1 1 : 0060 16 .............. 1 1 1 1 0 : 03c0 16 1 1 1 1 1 : 03e0 16 write 0 when writing. 0 is read when reading. o o o o : state remaining 000 w r
55 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group (6) endpoint 11 fig. 80 structure of ep11 set register fig. 81 structure of ep11 control register 1 fig. 82 structure of ep11 control register 2 b7 b0 not used sequence toggle bit clear bit not used transfer direction bit not used transfer type bite b2:b0 sqcl11 b4 dir11 b6 typ11 ep11 set register ( ep11cfg) [address 0019 16 ] 0 0 0 bit name bit symbol at reset function h/w s/w o o o o o o o o o o write 0 when writing. 0 is read when reading. 0 : toggle bit clear disabled 1 : writing 1 clears the toggle bit and data0 is used as the next data pid. 0 is always read when reading. write 0 when writing. 0 is read when reading. 0 : in transfer disabled 1 : in (data is transmitted to the host.) write 0 when writing. 0 is read when reading. 0 : transfer disabled 1 : interrupt transfer 0 00 00 w r : state remaining b7 b0 response pid bit not used pid11 [1:0] b7:b2 0 ep11 control register 1 ( ep11con1) [address 001a 16 ] bit name bit symbol at reset function h/w s/w b1 b0 0 0 : nak 0 1 : automatic response (nak, data0, data1) 1 x : stall write 0 when writing. 0 is read when reading. o o o o : state remaining 000000 w r b7 b0 b0val11 b7:b1 0 ep11 control register 2 ( ep11con2) [address 001b 16 ] bit name bit symbol at reset function h/w s/w o o o o : state remaining buffer 0 status bit not used this bit set to 1 shows the transmitting data is in a set state (sie is possible to read). write 0 when writing. 0 is read when reading. 00 0 00 0 0 w r
56 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group fig. 83 structure of ep11 interrupt source register fig. 84 structure of ep11 transmit byte number register fig. 85 structure of ep11 buffer area set register b7 b0 usb hub/endpoint 1 buffer 0 ready interrupt bit not used b0rdy11 b7:b1 0 0 ep11 interrupt source register (ep11req) [address 001d 16 ] bit name bit symbol at reset function h/w s/w o o o o 0: no interrupt request issued 1: interrupt request issued this bit is set to 1 when the buffer is ready state (enabled to be read/written) on usb hub/endpoint 1. 0 can be set by software, but 1 cannot be set. write 0 when writing. 0 is read when reading. : state remaining 0000000 w r b7 b0 b0byt11 b7:b1 0 ep11 transmit byte number register ( ep11byt0) [address 001e 16 ] in : set the transmitting byte number. write 0 when writing. 0 is read when reading. bit name bit symbol at reset function h/w s/w o o o o transmit byte number bit not used : state remaining 0000000 w r b7 b0 ep11 beginning address set bit not used badd11 [4:0] b7:b5 0 ep11 buffer area set register ( ep11buf) [address 0fed 16 ] bit name bit symbol at reset function h/w s/w set the beginning address of ep11 s buffer area. (32-byte unit) b4b3b2b1b0 0 0 0 1 0 : 0040 16 0 0 0 1 1 : 0060 16 .............. 1 1 1 1 0 : 03c0 16 1 1 1 1 1 : 03e0 16 write 0 when writing. 0 is read when reading. o o o o : state remaining 000 w r
57 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group hub function the 38k2 group has a hub function control circuit (hubfcc) that offers easy implementation of usb-hub functions (signal re- peat and bus state detection). this circuit is in compliance with usb specification version 2.0 full-speed/low-speed transfer modes (12 mbps/1.5 mbps, equivalent to version 1.1). the hubfcc operates with two external down-ports and one in- ternal down-port, which is utilized by the usb addresses of the built-in peripherals, enabling management of a total of three down- ports independently. a dedicated circuit automatically performs the bus state change detection and error detection needed for the sequence manage- ment of the hub repeater circuit, data repeat function, and down-port status management. this dedicated control circuit en- sures the user easy development of a program or timing design. fig. 86 hub functions cpu internal down- port external down-port (usb device) 38k2 group usb hub up-port (usb host) external down-port (usb device) each down-port register can be controlled by usb commands us- ing usb addresses for hub functions or detecting changes in the bus state of down-ports. the hubfcc is also equipped with a re- mote wakeup signal transfer function for use during global resume as other special signals management. the hubfcc generates an interrupt to the cpu when detecting a down-port state change (1 vector, 10 sources). the flexibility of the indispensable yet wide-ranging hubfcc structure and an external interrupt function and i/o ports imple- mented in the standard features of this mcu enable the power supply management essential for usb-hub functions and also al- low users to easily and effortlessly configure their optimum system.
58 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group hub function control circuit block diagram the hub function control circuit, as show in the diagram below, consists of the following blocks. (1) hub repeater block (2) down-port control block (3) cpu interface block (cif) (1) hub repeater block the hub repeater block, consisting of the circuits listed below, processes the hub repeater function sequence. the hub re- peater is ready for operation after enabling the usb module (usbe = ??. ?epeater circuit (detects sop/eop signal) ?rame-time circuit (synchronizes to sof signal and manages frames in 1 ms) ?eceiver circuit (manages up-port states) ?ransmitter circuit (controls up-port outputs) (2) down-port control block the down-port control block, consisting of the circuits listed below, performs down-port controls under supervision of the hub re- peater state operation. ?own-port sequencer circuit ?own-port state change detect circuit cpu cif hub function control circuit usb transceiver d0+ d0- usb down-port 1 transceiver hub repeater block down-port control block d1+ d1- usb down-port 2 transceiver d2+ d2- (3) cpu interface block (cif) the cpu interface block performs the following processes. control of repeater/down-port states through registers. generates interrupt signal controls internal bus interface fig. 87 hub function control circuit block diagram
59 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group usb down-port peripheral circuit setting the usb down-port peripheral circuits can be set with the down- stream port control register (address 0ff9 16 ). figures 88 and 89 show the circuit block diagrams. fig. 89 block diagram of usb down-port peripheral circuits (d2+, d2-) fig. 88 block diagram of usb down-port peripheral circuits (d1+, d1-) + - hub module d1+ d1- 27 ? pcon11 low speed pcon11 pcon10 pcon11 pcon10 pcon11 pcon10 pcon11 pcon10 full speed pcon11 pcon10 low speed pcon11 pcon10 full speed 27 ? + - d2+ d2- pcon21 low speed pcon21 pcon20 pcon21 pcon20 pcon21 pcon20 pcon21 pcon20 full speed pcon21 pcon20 low speed pcon21 pcon20 full speed hub module 27 ? 27 ?
60 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group interrupt request bit (ireq2: address 003d 16 ) usb hub hub interrupt bit (hubireq: address 0029 16 ) dp1 interrupt source at hub down-port 1 state change detected: disconnected state detected connected state detected port error state detected resume signal detected bus state change detected at hub down-port 2 state change detected: disconnected state detected connected state detected port error state detected resume signal detected bus state change detected hub interrupt function the hub function control circuit has one interrupt request consist- ing of 10 interrupt sources each of which can be determined through the interrupt source register. table 8 shows the hub inter- rupt sources. table 8 hub interrupt sources dp2 [dpxreg1] [dp1req] ptdis1 [dp2req] dp1 [hubireq] dp2 dp1e [hubicon] dp2e usb hub interrupt request ptcon1 pterr1 ptrsm1 ptchg1 ptdis2 ptcon2 pterr2 ptrsm2 ptchg2 fig. 90 usb hub interrupt control
61 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group hub register list the hub register list is shown below. fig. 91 hub related registers usb sfr symbol bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hubicon hubireq hubindex dpxreg1 dpxreg2 dpxreg3 dp1req dp1con dp1sts dp2req dp2con dp2sts dpctl 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002b 16 002c 16 002d 16 002b 16 002c 16 002d 16 0ff9 16 hub interrupt source enable register hub interrupt source register hub downstream port index register hub port field register 1 hub port field register 2 hub port field register 3 dp1 interrupt source register dp1 control register dp1 status register dp2 interrupt source register dp2 control register dp2 status register downstream port control register dp2e dp1e hrwu hrwue dp2 dp1 dpidx ptchg1 ptrsm1 pterr1 ptcon1 ptdis1 dslspd1 dsrmod1 dsrsmo1 dsrsto1 dsdete1 dssusp1 dspten1 dsconn1 d1plus d1minus ptchg2 ptrsm2 pterr2 ptcon2 ptdis2 dslspd2 dsrmod2 dsrsmo2 dsrsto2 dsdete2 dssusp2 dspten2 dsconn2 d2plus d2minus pcon2[1:0] pcon1[1:0] (1) hub port 1 (2) hub port 2 : not used address register name
62 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group hub related registers the hub related registers are shown below. fig. 92 structure of hub interrupt source enable register fig. 93 structure of hub interrupt source register b7 b0 dp1e dp2e b6:b2 hrwue 0 0 0 hub interrupt source enable register ( hubicon) [address 0028 16 ] bit name bit symbol at reset function h/w s/w o o o o o o o o hub downstream port 1 interrupt enable bit hub downstream port 2 interrupt enable bit not used hub upstream port remote- wakeup output enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled write 0 when writing. 0 is read when reading. 0 : disabled 1 : enabled : state remaining 00000 w r b7 b0 dp1 dp2 b6:b2 hrwu 0 0 0 hub interrupt source register ( hubireq) [address 0029 16 ] bit name bit symbol at reset function h/w s/w hub downstream port 1 interrupt bit hub downstream port 1 interrupt bit not used hub upstream port remote -wakeup output enable bit this bit is set to 1 when any one of dp1 interrupt source register s bits at least is set to 1 . this bit is cleared to 0 by clearing dp1 interrupt source register to 00 16 . writing to this bit causes no state change. this bit is set to 1 when any one of dp2 interrupt source register s bits at least is set to 1 . this bit is cleared to 0 by clearing dp2 interrupt source register to 00 16 . writing to this bit causes no state change. write 0 when writing. 0 is read when reading. 0 : remote-wakeup being not output 1 : remote-wakeup being output this bit change is not for a interrupt source. when detecting 2.5 s or more of k-signal on a downstream port in hub-suspended state, k-signal is output on from a upstream port and this bit is simultaneously set to 1 . 0 can be set by software, but 1 cannot be set. o o o o ? ? o o : state remaining 0 000 0 w r
63 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group b7 b0 dpidx b7:b1 0 hub downstream port index register (hubindex) [address 002a 16 ] bit name bit symbol at reset function h/w s/w o o o o : state remaining hub downstream port index bit not used 0 : hub downstream port 1 1 : hub downstream port 2 write 0 when writing. 0 is read when reading. 0000000 w r fig. 94 structure of hub downstream port index register
64 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group fig. 95 structure of dp1 interrupt source register (1) downstream port 1 b7 b0 ptdis1 ptcon1 pterr1 ptrsm1 ptchg1 b7:b5 0 0 0 0 0 dp1 interrupt source register ( dp1req) [address 002b 16 ] bit name bit symbol at reset function h/w s/w 000 downstream port 1 disconnect detection interrupt bit downstream port 1 connect detection interrupt bit downstream port 1 port error interrupt bit downstream port 1 resume interrupt bit downstream port 1 bus-change detection interrupt bit not used 0: no interrupt request issued 1: interrupt request issued this bit is set to 1 when detecting a bus-disconnect state (2.5 s or more of se0) on a do wnstream port 1 in dsconn1 = 1 . 0 can be set by software, but 1 cannot be set. 0: no interrupt request issued 1: interrupt request issued this bit is set to 1 when detecting a bus-connect state (2.5 s or more of j- or k- state) on a downstream port 1 in dsconn1 = 0 . 0 can be set by software, but 1 cannot be set. 0: no interrupt request issued 1: interrupt request issued this bit is set to 1 when an error occurs on a downstream port 1. 0 can be set by software, but 1 cannot be set. 0: no interrupt request issued 1: interrupt request issued this bit is set to 1 when detecting a resume signal on a downstream port 1 in the condition of hub suspended or port suspended state. 0 can be set by software, but 1 cannot be set. 0: no interrupt request issued 1: interrupt request issued this bit is set to 1 when detecting a bus-change of a downstream port 1 in the condition of hub suspended state. it is also 1 in the internal clock halted. 0 can be set by software, but 1 cannot be set. write 0 when writing. 0 is read when reading. o o o o o o o o o o o o : state remaining w r
65 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group b7 b0 dsconn1 dspten1 dssusp1 dsdete1 dsrsto1 dsrsmo1 dsrmod1 dslspd1 0 0 0 0 0 0 0 0 dp1 control register (dp1con) [address 002c 16 ] bit name bit symbol at reset function h/w s/w downstream port 1 connect bit downstream port 1 enable bit downstream port 1 suspend bit downstream port 1 connect- state detection enable bit downstream port 1 se0 signal transmit bit downstream port 1 resume signal transmit bit downstream port 1 bus-state read mode control bit downstream port 1 usb transfer 0 : disconnect ; ptcon1 interrupt enabled 1 : connect ; ptdis1 interrupt enabled 0 : downstream port 1 disabled 1 : downstream port 1 enabled ; this bit is cleared when an interrupt of ptdis1 or pterr1 is generated. 0 : no port suspended 1 : port suspended; this bit is cleared when an interrupt of ptdis1 or ptrsm1 is generated. 0 : connect/disconnect-state detection disabled ; ptcon1 and ptdis1 interrupts disabled 1 : connect/disconnect-state detection enabled ; this bit is cleared when an interrupt of ptcon1, ptdis1 or pterr1 is generated. 0 : being not output 1 : se0 signal being output 0 : being not output 1 : k-signal being output ; when writing 0 , a low-speed eop is output and then a transition to being not output occurs. 0 : mode where a downstream port 1 bus-state is read, using rd signal 1 : mode where a downstream port 1 bus-state is read, using eof2 signal (internal signal) 0 : full-speed mode (12mhz) 1 : low-speed mode (1.5 mhz) o o o o o o o o o o o o o o o o : state remaining w r fig. 96 structure of dp1 control register b7 b0 d1minus d1plus b7:b2 dp1 status register (dp1sts) [address 002d 16 ] bit name bit symbol at reset function h/w s/w : state remaining 000000 d1- signal bit d1+ signal bit not used in- definite in- definite in- definite in- definite o o o ? ? o in dsrmod1 = 0 , a downstream port 1 bus-state is read, using rd signal. in dsrmod1 = 1 , a downstream port 1 bus-state is read, using eof2 signal (internal signal). in dsrmod1 = 0 , a downstream port 1 bus-state is read, using rd signal. in dsrmod1 = 1 , a downstream port 1 bus-state is read, using eof2 signal (internal signal). write 0 when writing. 0 is read when reading. w r fig. 97 structure of dp1 status register
66 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group fig. 98 structure of dp2 interrupt source register (2) downstream port 2 b7 b0 ptdis2 ptcon2 pterr2 ptrsm2 ptchg2 b7:b5 0 0 0 0 0 dp2 interrupt source register ( dp2req) [address 002b 16 ] bit name bit symbol at reset function h/w s/w 000 downstream port 2 disconnect detection interrupt bit downstream port 2 connect detection interrupt bit downstream port 2 port error interrupt bit downstream port 2 resume interrupt bit downstream port 2 bus-change detection interrupt bit not used 0: no interrupt request issued 1: interrupt request issued this bit is set to 1 when detecting a bus-disconnect state (2.5 s or more of se0) on a do wnstream port 2 in dsconn2 = 1 . 0 can be set by software, but 1 cannot be set. 0: no interrupt request issued 1: interrupt request issued this bit is set to 1 when detecting a bus-connect state (2.5 s or more of j- or k- state) on a downstream port 2 in dsconn2 = 0 . 0 can be set by software, but 1 cannot be set. 0: no interrupt request issued 1: interrupt request issued this bit is set to 1 when an error occurs on a downstream port 2. 0 can be set by software, but 1 cannot be set. 0: no interrupt request issued 1: interrupt request issued this bit is set to 1 when detecting a resume signal on a downstream port 2 in the condition of hub suspended or port suspended state. 0 can be set by software, but 1 cannot be set. 0: no interrupt request issued 1: interrupt request issued this bit is set to 1 when detecting a bus-change of a downstream port 2 in the condition of hub suspended state. it is also 1 in the internal clock halted. 0 can be set by software, but 1 cannot be set. write 0 when writing. 0 is read when reading. o o o o o o o o o o o o : state remaining w r
67 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group fig. 99 structure of dp2 control register fig. 100 structure of dp2 status register b7 b0 dsconn2 dspten2 dssusp2 dsdete2 dsrsto2 dsrsmo2 dsrmod2 dslspd2 0 0 0 0 0 0 0 0 dp2 control register (dp2con) [address 002c 16 ] bit name bit symbol at reset function h/w s/w downstream port 2 connect bit downstream port 2 enable bit downstream port 2 suspend bit downstream port 2 connect- state detection enable bit downstream port 2 se0 signal transmit bit downstream port 2 resume signal transmit bit downstream port 2 bus-state read mode control bit downstream port 2 usb transfer speed select bit 0 : disconnect ; ptcon1 interrupt enabled 1 : connect ; ptdis1 interrupt enabled 0 : downstream port 2 disabled 1 : downstream port 2 enabled ; this bit is cleared when an interrupt of ptdis1 or pterr1 is generated. 0 : no port suspended 1 : port suspended; this bit is cleared when an interrupt of ptdis1 or ptrsm1 is generated. 0 : connect-state detection disabled ; ptcon1 and ptdis1 interrupts disabled 1 : connect-state detection enabled ; this bit is cleared when an interrupt of ptcon1, ptdis1 or pterr1 is generated. 0 : being not output 1 : se0 signal being output 0 : being not output 1 : k-signal being output ; when writing 0 , a low-speed eop is output and then a transition to being not output occurs. 0 : mode where a downstream port 2 bus-state is read, using rd signal 1 : mode where a downstream port 2 bus-state is read, using eof2 signal (internal signal) 0 : full-speed mode (12mhz) 1 : low-speed mode (1.5 mhz) o o o o o o o o o o o o o o o o : state remaining w r b7 b0 d2minus d2plus b7:b2 dp2 status register (dp2sts) [address 002d 16 ] bit name bit symbol at reset function h/w s/w : state remaining 000000 d2- signal bit d2+ signal bit not used in- definite in- definite in- definite in- definite o o o ? ? o in dsrmod2 = 0 , a downstream port 2 bus-state is read, using rd signal. in dsrmod2 = 1 , a downstream port 2 bus-state is read, using eof2 signal (internal signal). in dsrmod2 = 0 , a downstream port 2 bus-state is read, using rd signal. in dsrmod2 = 1 , a downstream port 2 bus-state is read, using eof2 signal (internal signal). write 0 when writing. 0 is read when reading. w r
68 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group fig. 101 structure of downstream port control register b7 b0 pcon1 [1:0] pcon2 [1:0] b7:b4 0 0 downstream port control register (dpctl) [address 0ff9 16 ] 0000 bit name bit symbol at reset function h/w s/w downstream port 1 function select bit downstream port 2 function select bit not used b1b0 0 0 : usb port (d1-, d1+) off, usb difference amplifier off 0 1 : usb exclusive input port (d1-, d1+), usb difference amplifier off 1 0 : full-speed port (d1-, d1+), usb difference amplifier on 1 1 : low-speed port (d1-, d1+), usb difference amplifier on b3b2 0 0 : usb port (d2-, d2+) off, usb difference amplifier off 0 1 : usb exclusive input port (d2-, d2+), usb difference amplifier off 1 0 : full-speed port (d2-, d2+), usb difference amplifier on 1 1 : low-speed port (d2-, d2+), usb difference amplifier on write 0 when writing. 0 is read when reading. o o o o o o : state remaining w r
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group 69 external bus interface (exb) the external bus interface (exb) controls the data transfer be- tween the external mcu and the 38k2 groups cpu or its cpu channel it is a data transfer course by the interrupt processing between the external mcu and the 38k2 groups cpu. memory channel it is a data transfer course by direct ram access of the memory channel controller between the external mcu and the 38k2 group? memory (multichannel ram) cpu channel [interrupt type] memory channel [direct ram access type] 38k2 group usb bus (usb host) external mcu cpu program rom peripheral functions external bus interface (exb) usb multichannel ram fig. 102 external bus interface address cs, rd, wr, dma acknowledge access cycle time from externals: 3 clocks or more of + signal delay time + data setup time of external mcu in usb inactive 5 clocks or more of + signal delay time + data setup time of external mcu in usb active fig. 103 data transfer timing of memory channel memory (multichannel ram). the external bus interface is shown below. data transfer of memory channel when the burst mode is selected with the burst bit of the memory channel operation mode register, data transfer can be carried out at the highest speed. after the external bus interface detects a rise of external read signal/write signal and synchronizes it with the in- ternal clock , it completes the data transfer between the transmit/ receive buffer and the multichannel ram in two clocks. however, the waiting time of two clocks at a maximum is gener- ated to access the multichannel ram in usb being operating because the usb has priority to access. therefore, it is necessary to set up the access interval which fills the following timing with the external mcu bus side. in = 8 mhz, data transfer at about 2 mbytes/second is possible at a maximum. when there is access simultaneously from the usb, it is about 1.3 mbytes/second. in = 6 mhz, data transfer at about 1.5 mbytes/second is possible at a maximum. when there is access simultaneously from the usb, it is about 1 mbytes/second.
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group 70 exb pin assignment the external bus interface (exb) pins are shown bellow. the 38k2 group can transmit/receive a data to/from an external mcu, using the following signals: control input signal ................ 4 (excs, exa0, exrd, exwr) data input/output pin .............. 8 (dq 0 to dq 7 ) interrupt output signal ............ 1 (exint) additionally, the dma interface signal and the buffer status read select signal of 38k2 group can be set up per one by the program. control input signal ................ 3 (extc, exdack, exrd, exa1) interrupt output signal ............ 1 (exdreq) external chip select external address external read external write external data external interrupt dma request terminal count dma acknowledge status read select external pins cpu multichannel ram external bus interface (exb) 38k2 group p3 4 /excs [ l ] p3 7 /exa0 [address] p3 6 /exrd [ l ] p3 5 /exwr [ l ] p1 0 /dq 0 /an 0 p1 7 /dq 7 /an 7 [data] p3 3 /exint [ l ] p4 0 /exdreq/rxd [ l ] p4 2 /extc/s clk [ l ] p4 1 /exdack/txd [ l ] p4 3 /exa 1 /s rdy [ h ] 8 : functions as normal ports just after reset. fig. 104 external bus interface (exb) pin assignment
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group 71 exb block diagram the block diagram of external bus interface (exb) is shown below. the external bus interface (exb) consists of: (1) external i/o interface part (2) cpu interface part (3) internal memory interface part (4) transmit/receive data buffer part external i/o interface cpu interface index register external i/o configuration register exb interrupt source enable register cch_wr external mcu bus cch_rd p3 4 /excs cpu channel txb_rdy controller rxb_rdy p3 7 /exa0 p3 6 /exrd memory channel control memory channel operation mode register memory channel transmit buffer control transmit buffer register receive buffer register memory channel controller end address register memory address counter memory channel status p3 5 /exwr mch_rd mch_wr mch_tc p4 1 /exdack/txd mrx_enb p4 2 /extc/s clk mtx_enb p4 3 /exa1/s rdy memory address request acknowledge memory read data memory write data p3 3 /exint mch_req p4 0 /exdreq/rxd fifo_stt mrdsel stt_sel buf_wr transmit/receive data buffer exoe p1 0 /dq 0 /an 0 p1 7 /dq 7 /an 7 multichannel ram command decoder output selector decoder data selector configuration signal internal memory interface : functions as normal ports just after reset. fig. 105 block diagram of external bus interface (exb)
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group 72 (1) external i/o interface part the external i/o interface part consists of a command decoder and an output selector. a command decoder generates the follow- ing signals to each unit. cpu interface part cpu channel read (cch_rd) cpu channel write (cch_wr) internal memory interface part memory channel read (mch_rd) memory channel write (mch_wr) memory channel terminal count (mch_tc) transmit/receive data buffer part buffer write (buf_wr) external i/o interface part status selection (stt_sel) output enable (exoe) access to the cpu channel can be controlled only by setup of external signals. access to the memory channel can be controlled by the value of the external i/o configuration register and the state (mrx_enb, mtx_enb signals) of the internal memory interface part. the output selector has the function which selects from the state of cpu channel (txb_rdy and rxd_rdy) and the state of memory channel (mch_req) as the signal assigned to p3 3 / exint pin and p4 0 /exdreq/rxd pin. (2) cpu interface part the cpu interface part consists of the decoder/data selector of the cpu channel, the cpu write register and cpu channel con- troller decoder/data selector of cpu channel a write operation to the cpu register is performed by generating a write signal for each register with an address decode signal and a write signal. a read operation from the cpu register is performed by generat- ing an output enable signal of the internal data bus with an module select signal and a read signal and generating a select signal for each register with an address decode signal. cpu write register there are three cpu write registers as follows: exb interrupt source enable register index register external i/o configuration register the exb interrupt source register is a read-only register. a status signal of the cpu channel controller and a status signal of the memory channel controller in the internal memory interface part are generated. cpu channel controller the cpu channel controller generates the following signals, using bits 0 and 1 (rxb_enb, txb_enb) of exb interrupt source en- able register. memory channel transmitting buffer control signal (mrd_sel), generated in the internal memory interface part cpu channel command signal (cch_rd, cch_wr), generated in the external i/o interface part signals rxb_rdy/rxb_full and txb_rdy/txb_empty, gener- ated with read/write signals from the cpu channel
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group 73 (3) internal memory interface part the internal memory interface part consists of the cpu register and the memory channel controller. cpu register the cpu register consists of the follows: memory channel operation mode register memory address counter end address register the cpu can set the beginning address into the memory address counter when the memory channel operation enable bit (mc_enb) of exb interrupt source enable register is 0 . when this bit is 1 , the write operation from the cpu is invalid and each access from the external bus causes count-up operation. memory channel controller the cpu register consists of the follows: main sequencer internal memory request signal generating circuit external memory channel request signal generating circuit address end detection circuit terminal end input processing circuit (4) transmit/receive data buffer part the transmit/receive data buffer part consists of the 8-bit transmit buffer register (txbuf) and the 8-bit receive buffer register (rxbuf). both cpu channel and memory channel use the same transmit buffer register/receive buffer register to transfer a data to an exter- nal mcu bus. (5) external pin the external bus interface has the following pins to connect with an external mcu bus. chip select ........................... p3 4 /excs address ................................ p3 7 /exa0 data ...................................... p1 0 /dq 0 /an 0 to p1 7 /dq 7 /an 7 read .................................... p3 6 /exrd write ..................................... p3 5 /exwr interrupt request .................. p3 3 /exint it also has the following pins to connect with an external dmac. each pin can be programmed for an ordinary port function or a dma interface pin function. dma request ........................ p4 0 /exdreq/rxd dma acknowledgment ......... p4 1 /exdack/txd terminal count ..................... p4 2 /extc/s clk it also has the status read select pin (p4 3 /exa1/s rdy pin) to con- firm a ready status of the data buffer from an external mcu bus this pin functions as a port just after reset. the status read select function can be set by a program. status read select ................ p4 3 /exa1/s rdy cpu channel: communication with 38k2 group cpu when a read/write operation is performed from an external mcu bus in address signal exa0 = h , the interrupt is generated and the 38k2 group cpu can confirm its access. the 38k2 group cpu judges the interrupt source and it starts a data transmission/recep- tion with an external mcu bus. memory channel: communication with 38k2 group memory multichannel ram when a read/write operation is performed from an external mcu bus in address signal exa0 = l , access to the multichannel ram is performed. then an address of the multichannel ram is made by the external bus interface and it is increased at each access completion. consequently, fifo access is performed. even if a read/write operation is performed in dack = l instead of excs = l and exa0 = l , fifo access to the multichannel ram is performed. the beginning address and the end address must be set by the cpu in advance.
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group 74 p3 3 /exint pin any one of the following signals for this pin can be selected: ?xb_rdy (transmit buffer ready) output ?xb_rdy (receive buffer ready) output ?ch_req (memory channel request) output either txb_rdy or rxb_rdy is normally selected. the memory channel request is for an access request signal to the memory channel. in a small system, a data transfer processing to the internal memory is performed in the interrupt routine. according to that situation, the 38k2 group has the function automatically to switch an interrupt factor attached on the interrupt pin by program. p4 0 /exdreq/rxd pin this pin is a port at the initial state. which signal can be set by program. ?xb_rdy (receive buffer ready) output ?ch_req (memory channel request) output mch_req of dmac is normally selected. the output method of the memory channel request signal depends on the burst bit (burst) of memory channel operation mode register. when the burst bit is ?? this signal is periodically output at each 1-byte transfer. (see figures 123 and 126.) when the burst bit is ?? this signal is continuously output while the memory address counter is counting from the beginning ad- dress to the end address (see figures 124 and 127.) p4 1 /exdack/txd pin this pin is a port at the initial state. the dma acknowledge signal can be set by program. the dma acknowledge signal dack = ??is the same state as that of cs = ??and a0 = ?? access to multichannel ram is started by a rise of read signal or write signal which is set during this term. note : if the dma acknowledge signal and the chip select signal are simultaneously active (dack = ??and cs = ??, also set the address signal a0 to ?? if a0 is ?? the memory channel and the cpu channel are activated simultaneously and it might cause some error. p4 2 /extc/s clk pin this pin is a port at the initial state. the terminal count signal can be set by program. if the terminal count signal is set at one bus cycle while a memory channel operation write is being performed, the 38k2 group con- firms that its bus cycle is the write cycle of the last data and sets the memory channel status bits to ?1 2 ? and the interrupt is gener- ated and the memory channel operation ends even if the memory address counter has not reached the end address. the cpu can obtain the last address where the data is written by reading out the value of memory address counter. (see figure 125.)
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group 75 exb register list the exb register list is shown below. fig. 106 exb related registers (1) exb interrupt source enable register this register enables/disables access from an external bus and an internal interrupt. ?xb interrupt source register this register indicates the state of cpu channel s transmit/receive buffer register and the memory channel. the same value can be read out from the external mcu bus by using the buffer status read select signal (a1 pin = h ). ?xb index register/register windows 1, 2 the accessible register is switched by treating addresses 0034 16 and 0035 16 as a register window depending on the value of exb index register at address 0033 16 . external i/o configuration register this register selects the function of each pin. transmit/receive buffer register this register consists of the receive buffer register (rxbuf) and the transmit buffer register (txbuf) memory channel operation mode register this register sets the operation mode of the memory channel. memory address counter this is a counter to set the beginning address which fifo ac- cesses. this register is increased by access from the external mcu bus. end address register this register is to set the end address which fifo accesses. mc_enb txb_enb rxb_emb mc_sts[1:0] txb_empty rxb_full index[2:0] 0 : 0 fixed : not used low_win[7:0] high_win[7:0] exb sfr symbol bit7 bit6 bit5 bit4 bit3 00000 bit2 bit1 bit0 exbicon exbireq exbindex exbreg1 exbreg2 0030 16 0031 16 0033 16 0034 16 0035 16 exb interrupt source enable register exb interrupt source register register window 1 (low) register window 2 (high) exb index register address register name index bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00 16 low low a1_ctr int_ctr[2:0] exb_ctr high high tc_ctr dak_ctr[1:0] drq_ctr[1:0] 01 16 low at cpu read : rxbuf[7:0] at cpu write : txbuf[7:0] high 02 16 low burst mc_dir[1:0] high 03 16 low im_a[7:0] high 00000 im_a[10:8] 04 16 low end_a[7:0] high 00000 end_a[10:8] external i/o configu- ration register transmit/receive buffer register memory channel ope- ration mode register memory address counter end address register exb sfr register name symbol exbcfgl exbcfgh rxbuf/txbuf mchmod memadl memadh endadl endadh 0 : 0 fixed : not used fig. 107 exb related registers (2)
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group 76 exb related registers the exb related registers are shown below. b7 b0 cpu channel receive enable bit cpu channel transmit enable bit memory channel operation enable bit not used rxb_enb txb_enb mc_enb b7:b3 0 0 0 e xb interrupt source enable register ( exbicon) [address 0030 16 ] ( note ) 00 000 bit name bit symbol at reset function h/w s/w 0 : operation disabled (interrupt disabled) 1 : operation enabled (receive buffer full interrupt enabled) 0 : operation disabled (interrupt disabled) 1 : operation enabled (transmit buffer empty interrupt enabled) 0 : operation disabled (memory channel operation end interrupt disabled) 1 : operation enabled (memory channel operation end interrupt disabled) write 0 when writing. 0 is read when reading. o o o o o o o o : state remaining w r note: do not set each bit simultaneously. fig. 108 structure of exb interrupt source enable register b7 b0 rxb_full txb_empty mc_sts [1:0] ( note 2 ) b7:b4 0000 0 0 0 0 (note 3) 0 (note 4) 0 e xb interrupt source register ( exbireq) [address 0031 16 ] ( note 1 ) bit name bit symbol at reset function h/w s/w o o o o o : state remaining receive buffer full bit transmit buffer empty bit memory channel status bits not used 0 : receive buffer empty 1 : receive buffer full 0 : transmit buffer full 1 : transmit buffer empty b3b2 0 0 : memory channel operation stopped 0 1 : memory channel being operating; no external access 1 0 : memory channel being operating; external accessing 1 1 : memory channel operation end; memory channel operation end interrupt generated write 0 when writing. 0 is read when reading. notes 1 : when the the exa1 pin control bit of external i/o configuration register is 1 , the external mcu bus can read this register contents by setting the exa1 pin to h . 2 : the memory channel status bits indicate the status of memory channel. in mc_enb = 0 these bits are always 00 2 . when the memory channel operation ends, these bits are set to 11 2 and the memory channel operation end interrupt is generated. these bits can be read out during operation, so that it will show that whether the external mcu bus is accessing or not. 3 : this bit is cleared to 0 when reading the transmit/receive buffer register in the cpu channel receive enable bit = 1 or when the cpu channel receive enable bit is 0 . 4 : this bit is cleared to 0 when writing to the transmit/receive buffer register in the cpu channel transmit enable bit = 1 or when the cpu channel transmit enable bit is 0 . w r fig. 109 structure of exb interrupt source register
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group 77 b7 b0 index [2:0] b7:b3 0 exb index register (exbindex) [address 0033 16 ] 00000 bit name bit symbol at reset function h/w s/w o o o o index bits not used the accessible register, using the register window, depends on these index bits contents as follows: b2b1b0 0 0 0 : external i/o configuration register 0 0 1 : transmit/receive buffer register 0 1 0 : memory channel operation mode register 0 1 1 : memory address counter 1 0 0 : end address register 1 0 1 : do not set. 1 1 0 : do not set. 1 1 1 : do not set. write 0 when writing. 0 is read when reading. : state remaining w r fig. 110 structure of exb index register b7 b0 low_win [7:0] in- definite in- definite register window 1 (exbreg1) [address 0034 16 ] bit name bit symbol at reset function h/w s/w oo the accessible register, using this register window, depends on the exb index register contents as follows: index value 00 16 : external i/o configuration register 01 16 : transmit/receive buffer register 02 16 : memory channel operation mode register 03 16 : memory address counter 04 16 : end address register w r b7 b0 high_win [7:0] in- definite in- definite register window 2 (exbreg2) [address 0035 16 ] bit name bit symbol at reset function h/w s/w oo the accessible register, using this register window, depends on the exb index register contents as follows: index value 00 16 : external i/o configuration register 01 16 : transmit/receive buffer register 02 16 : memory channel operation mode register 03 16 : memory address counter 04 16 : end address register w r fig. 111 structure of register window 1 fig. 112 structure of register window 2
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group 78 fig. 113 index00[low]; structure of external i/o configuration register fig. 114 index00[high]; structure of external i/o configuration register b7 b0 exb_ctr int_ctr [2:0] a1_ctr b7:b5 index = 00 16 : external i/o configuration register (exbcfgl) [address 0034 16 ] 0 0 0 000 bit name bit symbol at reset function h/w s/w 0 : port 1 : exb function pin selects a signal of p3 3 /exint pin. on/off is programmed by each bit. an output logical sum of p3 3 /exint pins set for on are performed and it is output as an l active signal. b3b2b1 0 0 1 : rxb_rdy (rxbuf ready) output 0 1 0 : txb_rdy (txbuf ready) output 1 0 0 : mch_req (memory channel request) output others : do not set. 0 : port 1 : a1 input (used to read status) write 0 when writing. 0 is read when reading. exb pin control bit (pins p1 0 to p1 7 , p3 0 to p3 4 ) p3 3 /exint pin control bit p4 3 /exa1 pin control bit not used o o o o o o o o : state remaining w r b7 b0 drq_ctr [1:0] dak_ctr [1:0] tc_ctr b7:b5 index = 00 16 : external i/o configuration register (exbcfgh) [address 0035 16 ] 0 0 0 000 bit name bit symbol at reset function h/w s/w b1b0 0 0 : port 0 1 : do not set. 1 0 : exdreq function; rxb_rdy (rxbuf ready) output 1 1 : exdreq function; mch_req (memory channel request) output specifies p4 1 /exdack/txd pin function. selects which mode; requiring read or write signal, or not requiring it for use of dma acknowledge function. b3b2 0 0 : port 0 1 : do not set. 1 0 : exdack function; dma acknowledge input (mode for read and write signals used together) 1 1 :exdack function; dma acknowledge input (mode for read and write signals not required) 0 : port 1 : extc (terminal count) input write 0 when writing. 0 is read when reading. p4 0 /exdreq/rxd pin control bit p4 1 /exdack/txd pin control bit p4 2 /extc/s clk pin control bit not used o o o o o o o o : state remaining w r
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group 79 fig. 115 index01[low]; structure of transmit/receive buffer register fig. 116 index02[low]; structure of memory channel operation mode register fig. 117 index03[low]; structure of memory address counter b7 b0 rxbuf/ txbuf 0 index =01 16 : transmit/receive buffer register (rxbuf/txbuf) [address 0034 16 ] bit name bit symbol at reset function h/w s/w oo the data received from an external bus is written here at the rise timing of external write signal. the data transmitted to an external bus is written here at the timing of internal cpu write or memory write. the receive buffer register (rxbuf) contents can be read out by reading to this address with the cpu. the data which the cpu has written to this address is stored in the transmit buffer register (txbuf). however, do not perform write operation with the cpu to this address if the memory channel direction control bits of memory channel operation mode register is 10 2 (transmit mode) and the memory channel status bits of exb interrupt source register are 01 2 or 10 2 (memory channel being operating). w r b7 b0 mc_dir [1:0] burst b7:b3 0 0 index =02 16 : memory channel operation mode register (mchmod) [address 0034 16 ] 00000 bit name bit symbol at reset function h/w s/w b1b0 0 0 : operation disabled 0 1 : receive mode 1 0 : transmit mode 1 1 : do not set. 0 : cycle mode (each byte transfer according to assertion or negation) 1 : burst mode (continuous transfer till the terminal count) write 0 when writing. 0 is read when reading. o o o o o o : state remaining memory channel direction control bit burst bit not used w r b7 b0 im_a [7:0] 0 index = 03 16 : memory address counter (memadl) [address 0034 16 ] bit name bit symbol at reset function h/w s/w oo register to set the low-order address of memory channel operation beginning. this contents are increased each time one memory access ends. w r
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group 80 fig. 118 index03[high]; structure of memory address counter fig. 119 index04[low]; structure of end address register fig. 120 index04[high]; structure of end address register b7 b0 im_a [10:8] b7:b3 0 index = 03 16 : memory address counter (memadh) [address 0035 16 ] 00000 bit name bit symbol at reset function h/w s/w o o o o : state remaining not used register to set the high-order address of memory channel operation start. this contents are increased each time one memory access ends. write 0 when writing. 0 is read when reading. w r b7 b0 end_a [7:0] 0 index = 04 16 : end address register (endadl) [address 0034 16 ] bit name bit symbol at reset function h/w s/w oo : state remaining register to set the low-order address of memory channel operation end. w r b7 b0 end_a [10:8] b7:b3 0 index = 04 16 : end address register (endadh) [address 0035 16 ] 00000 bit name bit symbol at reset function h/w s/w o o o o : state remaining not used register to set the high-order address of memory channel operation end. write 0 when writing. 0 is read when reading. w r
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group 81 exb operation timing diagram (1) cpu channel receiving operation cpu channel receiving operation is shown bellow. fig. 121 cpu channel receiving operation ??? address exa0 chip select excs a0 = 1 cs = 0 a0 = 1 cs = 0 read exrd ? write exwr data dq 0 to dq 7 #0 #1 internal clock interrupt request exint [rxb_rdy] rxb_rdy rxb_rdy receive buffer full bit rxb_full receive buffer rxbuf #0 #1 transmit buffer txbuf ? cpu channel receive enable bit rxb_enb receive buffer read ? external i/o configuration register int_ctr[3:1] (p3 3 /exint pin control) = 001 2 (rxb_rdy interrupt) exb interrupt source enable register rxb_enb (cpu channel receive enable) = 1 (receive buffer full interrupt enabled) ? writing the command for enabling operation makes rxb_rdy assertion and the p3 3 /exint pin goes to l . if the cpu channel receive enable bit (rxb_enb) is 0 , both the receive buffer full bit (rxb_full) and the receive buffer ready signal (rxb_rdy) to an external are inactive. ? when a write operation is performed from an external mcu bus in the condition of excs = l and wxa0 = h , it will result in as follows: the data is written into the receive buffer (rxbuf) negation of the receive buffer ready signal (rxb_rdy) to an external is made the rxb_full interrupt is generated. ? when the cpu reads out the receive buffer (rxbuf) with an interrupt processing program, the receive buffer full bit (rxb_full) is cleared to 0 .
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group 82 (2) cpu channel transmitting operation cpu channel transmitting operation is shown bellow. fig. 122 cpu channel tranmitting operation #0 #1 txb_rdy txb_rdy #0 #1 ? ? ? ? ? ? ? ? address exa0 chip select excs read exrd write exwr data dq 0 to dq 7 internal clock interrupt request exint [txb_rdy] transmit buffer empty bit txb_empty receive buffer rxbuf transmit buffer txbuf cpu channel transmit enable bit txb_enb transmit data write external i/o configuration register int_ctr[3:1] (p3 3 /exint pin control) = 010 2 (txb_rdy interrupt) exb interrupt source enable register txb_enb (cpu channel transmit enable) = 1 (transmit buffer empty interrupt enabled) ? writing the command for enabling operation generates txb_empty interrupt. if the cpu channel transmit enable bit (txb_enb) is 0 , both the transmit buffer empty bit (txb_empty) and the transmit buffer ready signal (txb_rdy) to an external are inactive. ? when the cpu writes the data into the transmit buffer (txbuf) with an interrupt processing program, the transmit buffer empty bit (txb_empty) is cleared to 0 and assertion of the transmit buffer ready signal (txb_rdy) to an external is made. ? when a read operation is performed from an external mcu bus in the condition of excs = l and exa0 = h , it will result in as follows: the contents of the transmit buffer (txbuf) is read out the transmit buffer empty bit (txb_empty) is set to 1 negation of the transmit buffer ready signal (txb_rdy) to an external is made. a0 = 1 cs = 0 a0 = 1 cs = 0
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group 83 (3) memory channel receiving operation (1)- cycle mode memory channel receiving operation (1) is shown bellow. fig. 123 memory channel receiving operation (1) dma acknowledge exdack #0 #1 mch_req mch_req mwr detection mwr detection #0 #1 012 3 5 req req 0100 16 0101 16 0102 16 ack ack dma request exdreq ? ? ?? ? ?? ? ? ? address exa0 chip select excs read exrd write exwr data dq 0 to dq 7 internal clock receive buffer rxbuf operation enabled main sequencer internal memory access acknowledgment of internal memory access memory address counter end memory channel operation end interrupt ? ? a0 = 0 cs = 0 a0 = 0 cs = 0 external i/o configuration register set as necessary. memory channel operation mode register mc_dir[1:0] (memory channel direction control) = 01 2 (receive mode) burst (burst) = 0 (cycle mode) memory address counter (example) 0100 16 end address register (example) 0101 16 exb interrupt source enable register mc_enb (memory channel operation enable) = 1 (operation start) ? in the memory channel receive mode when the command for enabling operation is written, operation starts (main sequencer starts ) and assertion of the memory channel request which synchronized with a rise of is made. ? when the external mcu bus is in the condition of excs = l and exa0 = l or a fall of exwr is detected in the condition of exdack = l , negation of the memory channel request which synchronized with a rise of is made. ? when a rise of exwr is detected, an internal memory access sequence which synchronized with a rise of is activated and a data is written in the internal memory within two clocks at a minimum. ? the memory address counter is increased simultaneously at write completion and assertion of the next memory channel request is made. ? when the write operation to the end address has been completed, the memory address counter is increased, but assertion of the next memory channel request is not made and the memory channel operation end interrupt is generated.
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group 84 (4) memory channel receiving operation (2)- burst mode memory channel receiving operation (2) is shown bellow. fig. 124 memory channel receiving operation (2) dack = 0 dack = 0 dack = 0 #0 #1 #2 mch_req #0 #1 #2 012 3 5 req req req 0100 16 0101 16 0102 16 0103 16 ack ack ack dma acknowledge exdack mwr detection mwr detection dma request exdreq ? ? ? ? ? ? ??? ??? address exa0 chip select excs read exrd write exwr data dq 0 to dq 7 internal clock operation enabled main sequencer internal memory access acknowledgment of internal memory access memory address counter end burst end memory channel operation end interrupt ? ? a0 = x cs = 1 a0 = x cs = 1 a0 = x cs = 1 external i/o configuration register set as necessary. memory channel operation mode register mc_dir[1:0] (memory channel direction control) = 01 2 (receive mode) burst (burst) = 1 (burst mode) memory address counter (example) 0100 16 end address register (example) 0102 16 exb interrupt source enable register mc_enb (memory channel operation enable) = 1 (operation start) ? in the memory channel receive mode when the command for enabling operation is written, assertion of the memory channel request which synchronized with a rise of is made. ? when a rise of exwr is detected, an internal memory access sequence which synchronized with a rise of is activated and a data is written in the internal memory within two clocks at a minimum. ? the memory address counter is increased simultaneously at the former data write completion. ? when the memory address counter reaches the end address, the detection circuit of external write signal (exwr) operation is e nabled and negation of the memory channel request which synchronized with the following is made. ? when the write operation to the end address has been completed, the memory address counter is increased and the memory channel operation end interrupt is generated. receive buffer rxbuf
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group 85 (5) memory channel receiving operation (3)- burst mode (terminal count) memory channel receiving operation (3) is shown bellow. fig. 125 memory channel receiving operation (3) tc #0 #1 mch_req #0 #1 012 3 (5) 5 req 0100 16 0101 16 0102 16 ack ack dma acknowledge exdack mwr detection mwr detection dma request exdreq ? ? ? ? ? ? ? ? ? ? ? ? address exa0 chip select excs terminal count extc write exwr data dq 0 to dq 7 internal clock operation enabled receive buffer rxbuf tc synchronizing tc end main sequencer internal memory access memory address counter end burst end memory channel operation end interrupt ? mtc detection ? ? external i/o configuration register set as necessary. memory channel operation mode register mc_dir[1:0] (memory channel direction control) = 01 2 (receive mode) burst (burst) = 1 (burst mode) memory address counter (example) 0100 16 end address register (example) 0107 16 exb interrupt source enable register mc_enb (memory channel operation enable) = 1 (operation start) ? when a rise of tc is detected, negation of the memory channel request which synchronized with a rise of is made. ? when the write operation to the end address has been completed, the memory channel operation end interrupt is generated. acknowledgment of internal memory access dack = 0 a0 = x cs = 1 dack = 0 a0 = x cs = 1
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group 86 fig. 126 memory channel tranmitting operation (1) (6) memory channel transmitting operation (1)-cycle mode memory channel transmitting operation (1) is shown bellow. #0 #1 mch_req mch_req #0 #1 012 34 5 req req 0100 16 0101 16 0102 16 ack ack dma acknowledge exdack mrd detection mrd detection dma request exdreq ? ? ? ? ? ?? ?? ? ? ? ? ? address exa0 chip select excs read exrd write exwr data dq 0 to dq 7 internal clock transmit buffer txbuf operation enabled transmission completed main sequencer internal memory access acknowledgment of internal memory access memory address counter end memory channel operation end interrupt ? ? dack = 0 a0 = x cs = 1 dack = 0 a0 = x cs = 1 external i/o configuration register set as necessary. memory channel operation mode register mc_dir[1:0] (memory channel direction control) = 10 2 (transmit mode) burst (burst) = 0 (cycle mode) memory address counter (example) 0100 16 end address register (example) 0101 16 exb interrupt source enable register mc_enb (memory channel operation enable) = 1 (operation start) ? in the memory channel transmit mode when the command for enabling operation is written, operation starts (main sequencer start s) and an internal memory access sequence which synchronized with a rise of is activated. ? a data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer (txb uf). the memory address counter is simultaneously increased and assertion of the memory channel request is made. ? when the external mcu bus is in the condition of excs = l and exa0 = l or a fall of exrd is detected in the condition of exdack = l , negation of the memory channel request which synchronized with a rise of is made. ? when a rise of exrd is detected, an internal memory access sequence which synchronized with a rise of is activated. ? a data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer (txb uf). the memory address counter is simultaneously increased and assertion of the memory channel request is made. when the read operation from the end address has been completed, the transition to the status to wait the memory channel operat ion end occurs. ? when a rise of exrd is detected, the memory channel operation sequence ends and the memory channel operation end interrupt is generated.
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group 87 fig. 127 memory channel tranmitting operation (2) (7) memory channel transmitting operation (2)-burst mode memory channel transmitting operation (2) is shown bellow. #0 #1 #2 mch_req #0 #1 #2 012 3 4 5 req req req 0100 16 0101 16 0102 16 0103 16 ack ack ack dma acknowledge exdack mrd detection mrd detection dma request exdreq ? ? ?? ? ? ? ?? ??? ? ? address exa0 chip select excs read exrd write exwr data dq 0 to dq 7 internal clock transmit buffer txbuf operation enabled transmission completed main sequencer internal memory access acknowledgment of internal memory access memory address counter end burst end memory channel operation end interrupt ? ? external i/o configuration register set as necessary. memory channel operation mode register mc_dir[1:0] (memory channel direction control) = 10 2 (transmit mode) burst (burst) = 1 (burst mode) memory address counter (example) 0100 16 end address register (example) 0102 16 exb interrupt source enable register mc_enb (memory channel operation enable) = 1 (operation start) ? in the memory channel transmit mode when the command for enabling operation is written, an internal memory access sequence whi ch synchronized with a rise of is activated. ? a data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer (txb uf). the memory address counter is simultaneously increased and assertion of the memory channel request is made. ? when a rise of exrd is detected, an internal memory access sequence which synchronized with a rise of is activated. ? a data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer (txb uf). the memory address counter is simultaneously increased. ? when the read operation from the end address has been completed, the detection circuit of external read signal (exrd) operatio n is enabled and negation of the memory channel request which synchronized with the following is made. ? when a rise of exrd is detected, the memory channel operation sequence ends and the memory channel operation end interrupt is generated. dack = 0 a0 = x cs = 1 dack = 0 a0 = x cs = 1 dack = 0 a0 = x cs = 1
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group 88 multichannel ram the 38k2 group has the built-in multichannel ram including the small logic circuit (ram i/f) instead of ordinary ram. the multichannel ram has the usb channel and the exb channel in addition to the cpu channel. the multichannel ram controls access from cpu, usb and exb, synchronizing control with . the usb transfer rate is about 1.5 mbytes/second. access to the multichannel ram is performed at every about 5.3 clocks in = 8 mhz, or at every about 4 clocks in = 6 mhz. the usb s access has priority to the exb s. the one wait function (onw function) of 38000 series cpu is used internally to control access with the cpu. when receiving an access request from the usb or the exb, the multichannel ram outputs onw signal to wait the cpu for one clock, and access of the usb or the exb is performed. if the multichannel ram is outputting onw signal while the cpu is in the state of reading/writing for the ram area, the cpu read cycle or write cycle is extended by 1 period of . fig. 128 multichannel ram timing diagram (no wait) cpu ad rd/wr usb req exb req onw ram access right ram rd/wr cpu bus cycle multichannel ram ram bus cycle cpu usb cpu ram area except ram ram area no wait no wait no wait except ram no rd/wr cpu ad rd/wr usb req exb req onw ram access right ram rd/wr o ne wa i t 2-cycle wait (max.) for exb prior cpu prior cpu prior usb ram area o ne wa i t usb having priority of usb/exb simultaneous access prior cpu ram area cpu cpu cpu exb cpu usb usb ram area exb multichannel ram ram bus cycle cpu bus cycle o ne wa i t prohibiting continuous access of usb/exb cpu accessing ram at the latter part o ne wa i t ram area fig. 129 multichannel ram timing diagram (one wait) onw = h
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group 89 multichannel ram operation example the multichannel ram operation example is shown below. this example shows the case that an external mcu uses the 38k2 group as a peripheral lsi (usb controller). the following explains that the external mcu reads out the data which is received via the usb. ? the data which is received via the usb is written into the multi- channel ram. ? receive completion is propagated to the cpu. ? the external bus interface is activated owing to the cpu. ? (1) the external bus interface sets the data which is read from the multichannel ram into the internal data buffer. (2) the external mcu reads out the data bus buffer of the exter- nal bus interface. (3) the above operation is repeated by the number of the re- ceived bytes. after that, the data transfer is completed. fig. 130 multichannel ram operation example cpu usb external mcu external mcu bus usb bus (usb host) program rom peripheral functions external bus interface multichannel ram ? activating ? fifo read of received data by external bus interface ? fifo write of received data by usb ? notice of receive completion
90 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group a-d converter the functional blocks of the a-d converter are described below. [a-d conversion register 1, 2 (ad1, ad2)] 0037 16 , 0038 16 the a-d conversion register is a read-only register that stores the result of an a-d conversion. when reading this register during an a-d conversion, the previous conversion result is read. bit 7 of the a-d conversion register 2 must be set to ??not only 10-bit reading but also only high-order 8-bit reading of conversion result can be performed by selecting the reading procedure of the a-d conversion registers 1, 2 after a-d conversion is completed (in figure 132). the 8-bit reading inclined to msb is performed when reading the a-d converter register 1 after a-d conversion is started or reset; and when the a-d converter register 1 is read after reading the a- d converter register 2, the 8-bit reading inclined to lsb is performed. [a-d control register (adcon)] 0036 16 the a-d control register controls the a-d conversion process. bits 0 to 2 select a specific analog input pin. bit 3 signals the comple- tion of an a-d conversion. the value of this bit remains at ? during an a-d conversion, and changes to ??when an a-d con- version ends. writing ??to this bit starts the a-d conversion. comparison voltage generator the comparison voltage generator divides the voltage between v ref and av ss into 1024, and that outputs the comparison volt- age. the a-d converter successively compares the comparison voltage v ref in each mode, dividing the v ref voltage (see below), with the input voltage. 10-bit reading v ref = ? n (n = 0?023) 8-bit reading v ref = ? n (n = 0?55) channel selector the channel selector selects one of the input ports p1 7 /an 7 ?1 0 / an 0 . comparator and control circuit the comparator and control circuit compares an analog input volt- age with the comparison voltage, and then stores the result in the a-d conversion registers 1, 2. when an a-d conversion is com- pleted, the control circuit sets the ad conversion completion bit and the ad interrupt request bit to ?? note that because the comparator consists of a capacitor cou- pling, set f(system clock) to 500 khz or more during an a-d conversion. fig. 131 structure of a-d control register v ref 256 v ref 1024 fig. 132 10-bit/8-bit reading a - d c o n t r o l r e g i s t e r ( a d c o n : a d d r e s s 0 0 3 6 1 6 ) ad convers i on comp l et i on bi t 0 : conversion in progress 1 : conversion completed a n a l o g i n p u t p i n s e l e c t i o n b i t s 0 0 0 : p 1 0 / d q 0 / a n 0 0 0 1 : p 1 1 / d q 1 / a n 1 0 1 0 : p 1 2 / d q 2 / a n 2 0 1 1 : p 1 3 / d q 3 / a n 3 1 0 0 : p 1 4 / d q 4 / a n 4 1 0 1 : p 1 5 / d q 5 / a n 5 1 1 0 : p 1 6 / d q 6 / a n 6 1 1 1 : p 1 7 / d q 7 / a n 7 n o t u s e d ( i n d e f i n i t e a t r e a d ) ( t h e s e b i t s a r e w r i t e d i s a b l e d b i t s . ) b 7 b 0 10-bit reading (read address 0038 16 before 0037 16 ) note : bits 2 to 7 of address 0038 16 become 0 at reading. b 8 b 7 b 6 b 5 b4 b3 b 2 b1 b0 b 7 b0 b 9 b7 b 0 b 9 b 8 b 7 b6 b5 b 4 b 3 b2 b7 b 0 0 ( a d d r e s s 0 0 3 8 1 6 ) (a d d r e s s 0 0 3 7 1 6 ) 8-bit reading (read only address 0037 16 ) (address 0037 16 )
91 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group fig. 133 a-d converter block diagram p 1 0 / d q 0 / a n 0 p 1 1 / d q 1 / a n 1 p 1 2 / d q 2 / a n 2 p 1 3 / d q 3 / a n 3 p 1 4 / d q 4 / a n 4 p 1 5 / d q 5 / a n 5 p 1 6 / d q 6 / a n 6 p 1 7 / d q 7 / a n 7 d a t a b u s a - d c o n t r o l r e g i s t e r ( a d d r e s s 0 0 3 6 1 6 ) v ss b 7b 0 3 1 0 a-d control circuit comparator r e s i s t o r l a d d e r a-d conversion register 2 a-d conversion register 1 (address 0038 16 ) (address 0037 16 ) c h a n n e l s e l e c t o r a - d i n t e r r u p t r e q u e s t v ref
92 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group fig. 135 structure of watchdog timer control register fig. 134 block diagram of watchdog timer watchdog timer the watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, be- cause of a software run-away). the watchdog timer consists of an 8-bit watchdog timer l and an 8-bit watchdog timer h. standard operation of watchdog timer when any data is not written into the watchdog timer control reg- ister (address 0039 16 ) after resetting, the watchdog timer is in the stop state. the watchdog timer starts to count down by writing an optional value into the watchdog timer control register (address 0039 16 ) and an internal reset occurs at an underflow of the watch- dog timer h. accordingly, programming is usually performed so that writing to the watchdog timer control register (address 0039 16 ) may be started before an underflow. when the watchdog timer control reg- ister (address 0039 16 ) is read, the values of the high-order 6 bits of the watchdog timer h, stp instruction disable bit (bit 6), and watchdog timer h count source selection bit (bit 7) are read. initial value of watchdog timer at reset or writing to the watchdog timer control register (address 0039 16 ), each watchdog timer h and l is set to ff 16 . watchdog timer h count source selection bit operation bit 7 of the watchdog timer control register (address 0039 16 ) per- mits selecting a watchdog timer h count source. when this bit is set to 0 , the count source becomes the underflow signal of watchdog timer l. the detection time is set to 131.072 ms at sys- tem clock 8 mhz frequency. when this bit is set to 1 , the count source becomes the system clock divided by 16. the detection time in this case is set to 512 s at system clock 8 mhz frequency. this bit is cleared to 0 after resetting. operation of stp instruction disable bit bit 6 of the watchdog timer control register (address 0039 16 ) per- mits disabling the stp instruction when the watchdog timer is in operation. when this bit is 0 , the stp instruction is enabled. when this bit is 1 , the stp instruction is disabled. once the stp instruction is executed, an internal reset occurs. when this bit is set to 1 , it cannot be rewritten to 0 by program. this bit is cleared to 0 after resetting. s y s t e m c l o c k 0 1 1 / 1 6 reset f f 1 6 i s s e t w h e n w a t c h d o g t i m e r c o n t r o l r e g i s t e r i s w r i t t e n t o . w a t c h d o g t i m e r l ( 8 ) watchdog timer h count source selection bit w a t c h d o g t i m e r h ( 8 ) d a t a b u s f f 1 6 i s s e t w h e n w a t c h d o g t i m e r c o n t r o l r e g i s t e r i s w r i t t e n t o . s t p i n s t r u c t i o n d i s a b l e b i t s t p i n s t r u c t i o n r e s e t c i r c u i t internal reset b0 stp instruction disable bit 0: stp instruction enabled 1: stp instruction disabled watchdog timer h count source selection bit 0: watchdog timer l underflow 1: system clock/16 watchdog timer h (for read-out of high-order 6 bit) watchdog timer control register (wdtcon : address 0039 16 ) b 7
93 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group fig. 136 example of reset circuit reset circuit to reset the microcomputer, reset pin should be held at an l level for 16 cycles or more of x in . then the reset pin is returned to an h level (the power source voltage should be between 3.0 v and 5.25 v, and the oscillation should be stable), reset is released. after the reset is completed, the program starts from the address contained in address fffd 16 (high-order byte) and address fffc 16 (low-order byte). make sure that the reset input voltage is 0.6 v for v cc of 3.0 v. fig. 137 reset sequence 0 v 0 v v c c r e s e t v c c r e s e t ( n o t e ) 0 . 2 v c c p o w e r o n p o w e r s o u r c e v o l t a g e d e t e c t i o n c i r c u i t p o w e r s o u r c e v o l t a g e r e s e t i n p u t v o l t a g e note : reset release voltage ; vcc = 3.0 v r e s e t i n t e r n a l r e s e t d a t a a d d r e s s s y n c x i n : 1 0 . 5 t o 1 8 . 5 c l o c k c y c l e s x i n ? ? ? ? ? f f f cf f f d a d h , l ? ? ? ? ? a d l a d h 1 : t h e f r e q u e n c y r e l a t i o n o f f ( x i n ) a n d f ( ) i s f ( x i n ) = 8 f ( ) . 2 : t h e q u e s t i o n m a r k s ( ? ) i n d i c a t e a n u n d e f i n e d s t a t e t h a t d e p e n d s o n t h e p r e v i o u s s t a t e . r e s e t a d d r e s s f r o m t h e v e c t o r t a b l e . n o t e s
94 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group pll circuit (frequency synthesizer) the pll circuit generates f vco (pll output clock), which is re- quired for f usb (usb clock) and f syn (f usb division clock), from f(x in ) (external input reference clock). figure 138 shows the pll circuit block diagram. it is possible to input 6 or 12 mhz clock from the externals as a standard clock input. when using the usb function, set the pll operation mode selection bit so that fvco may be set to 48 mhz. the pll circuit operates by setting the pll operation enable bit to 1 . when supplying f vco to the usb block, wait for the oscillation stable time (1ms or less) of pll before selecting f vco with the usb clock selection bit. according to the setting of the usb clock division ratio selection bit, the division clock of f usb is supplied to f syn . when using this clock as system clock, set the usb clock division ratio selection bit so that it may be set to 6 mhz, 8 mhz or 12 mhz. (however, using it only when f usb is 48mhz is recommended). fig. 138 block diagram of pll circuit pll f usb f ( x i n ) f v c o p l l c o n d i v i s i o n c i r c u i t f syn (address 0ff8 16 ) usbcon (address 0010 16 )
95 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group fig. 139 structure of pll control register pll control register (pllcon: address 0ff8 16 ) n o t u s e d ( r e t u r n 0 w h e n r e a d ) u s b c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t s b 4 b 3 0 0 : d i v i d e d b y 8 ( f s y n = f u s b / 8 ) 0 1 : d i v i d e d b y 6 ( f s y n = f u s b / 6 ) 1 0 : d i v i d e d b y 4 ( f s y n = f u s b / 4 ) 1 1 : n o t s e l e c t e d p l l o p e r a t i o n m o d e s e l e c t i o n b i t s b 6 b 5 0 0 : n o t m u l t i p l i e d ( f v c o = f x i n ) 0 1 : d o u b l e ( f v c o = f x i n ? 2 ) 1 0 : q u a d r u p l e ( f v c o = f x i n ? 4 ) 1 1 : m u l t i p l i e d b y 8 ( f v c o = f x i n ? 8 ) p l l e n a b l e b i t 0 : d i s a b l e d 1 : e n a b l e d b 0 b 7
96 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group clock generating circuit an oscillation circuit can be formed by connecting a resonator be- tween x in and x out . use the circuit constants in accordance with the resonator manufacturer s recommended values. no external resistor is needed between x in and x out since a feed-back resis- tor exists on-chip. frequency control either f syn or f(x in ) can be selected as an internal system clock. furthermore, the frequency of internal clock can be selected by the system clock division ratio selection bit. (1) f syn clock f syn clock is generated by the pll circuit. f(x in ) or f vco can be selected as an input clock. when using as an internal system clock, there is restriction on use. refer to the clause of pll cir- cuit . (2) f(x in ) clock the frequency applied to the x in pin is used as an internal system clock frequency. oscillation control (1) stop mode if the stp instruction is executed, the internal clock stops at an h level, and the x in oscillator stops. when the oscillation stabi- lizing time set after stp instruction released bit is 0, the prescaler 12 is set to ff 16 and timer 1 is set to 01 16 . when the oscillation stabilizing time set after stp instruction released bit is 1, set the sufficient time for oscillation of used oscillator to stabi- lize since nothing is set to the prescaler 12 and timer 1. x in divided by 16 is compulsorily connected to the input of the prescaler 12. oscillator restarts when an external interrupt (includ- ing usb resume interrupt) is received, but the internal clock remains at h until timer 1 underflows. the internal clock is not supplied until timer 1 underflows. because the sufficient time is re- quired for the oscillation to stabilize when a ceramic resonator etc. is used. when the oscillator is restarted by reset, apply l level to the reset pin until the oscillation is stable since a wait time will not be generated automatically. (2) wait mode if the wit instruction is executed, the internal clock stops at an h level, but the oscillator does not stop. the internal clock re- starts at reset or when an interrupt is received. since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. to ensure that the interrupts will be received to release the stp or wit state, their interrupt enable bits must be set to 1 before ex- ecuting of the stp or wit instruction. when releasing the stp state, the prescaler 12 and timer 1 will start counting the clock x in divided by 16. accordingly, set the timer 1 interrupt enable bit to 0 before executing the stp instruc- tion. note when using the oscillation stabilizing time set after stp instruction released bit set to 1 , evaluate time to stabilize oscillation of the used oscillator and set the value to the timer 1 and prescaler 12.
97 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group fig. 143 system clock generating circuit block diagram (single-chip mode) fig. 140 ceramic resonator or quartz-crystal oscilltor circuit fig. 141 external clock input circuit fig. 142 structure of misrg c i n c o u t x i n x o u t x o u t e x t e r n a l o s c i l l a t i o n c i r c u i t o p e n v cc v ss x i n m i s r g ( m i s r g : a d d r e s s 0 f f b 1 6 ) o s c i l l a t i o n s t a b i l i z i n g t i m e s e t a f t e r s t p i n s t r u c t i o n r e l e a s e d b i t 0 : a u t o m a t i c a l l y s e t 0 1 1 6 t o t i m e r 1 , f f 1 6 t o p r e s c a l e r 1 2 1 : a u t o m a t i c a l l y s e t n o t h i n g n o t u s e d ( i n d e f i n i t e a t r e a d ) b 0 b 7 p l l 1 / 8 1 / 41 / 6 f u s b x i n x o u t f s i o f a d 1 / 8 1 / 4 1 / 2 1 / 1 s r q s r q s r q 1 / 2 f f 1 6 0 1 1 6 1 / 2 1 / 2 1 / 2 f v c o f s y n u s b c l o c k s e l e c t i o n b i t u s b c l o c k d i v i s i o n r a t i o n s e l e c t i o n b i t s s y s t e m c l o c k d i v i s i o n r a t i o n s e l e c t i o n b i t s t i m e r 1 p r e s c a l e r 1 2 r e s e t o r s t p i n s t r u c t i o n t i m i n g ( i n t e r n a l c l o c k ) s t p i n s t r u c t i o n w i t i n s t r u c t i o n s t p i n s t r u c t i o n r e s e t i n t e r r u p t r e q u e s t i n t e r r u p t d i s a b l e f l a g l s y s t e m c l o c k s e l e c t i o n b i t
98 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38k2 group note s r e s e t c m 7 1 0 cm6 0 1 x i n 8 - d i v i d e m o d e f ( ) = 0 . 7 5 m h z c m 7 = 0 c m 6 = 0 c m 5 = 0 p l l c o n [ 4 : 3 ] = 0 0 1 : s w i t c h t h e m o d e b y t h e a l l o w s s h o w n b e t w e e n t h e m o d e b l o c k s . ( d o n o t s w i t c h b e t w e e n t h e m o d e s d i r e c t l y w i t h o u t a n a l l o w . ) 2 : s e t t h e u s b c l o c k ( f u s b ) t o 4 8 m h z w h e n s w i t c h i n g t h e s y s t e m c l o c k t o f s y n . 3 : d o n o t c h a n g e a d i v i s i o n r a t i o o f u s b c l o c k w h e n u s i n g f s y n a s t h e s y s t e m c l o c k . 4 : s e e s e c t i o n p l l c i r c u i t i n d e t a i l s f o r e n a b l i n g / d i s a b l i n g p l l o p e r a t i o n a n d u s a g e n o t e s o f f s y n . 5 : s e t t h e s y s t e m c l o c k t o x i n w h e n e n t e r i n g s t o p m o d e . 6 : i n a l l m o d e s , s w i t c h i n g t o w a i t m o d e i s p o s s i b l e . w h e n i t i s r e l e a s e d , t h e m c u r e t u r n s t o t h e o r i g i n a l m o d e . i n w a i t m o d e t h e t i m e r s c a n o p e r a t e . c m 5 1 0 remarks : this diagram assumes that the 6 mhz signals are applied to x in pin. x in 4-divide mode f( ) = 1.5 mhz cm7 = 0 cm6 = 0 cm5 = 0 pllcon [4:3] = xx (arbitrary) c m 7 1 0 c m 6 0 1 c m 7 0 1 c m 6 0 1 c m 7 1 0 x i n 2 - d i v i d e m o d e f ( ) = 3 . 0 m h z c m 7 = 1 c m 6 = 0 c m 5 = 0 p l l c o n [ 4 : 3 ] = x x ( a r b i t r a r y ) cm6 0 1 x in through mode f( ) = 1.5 mhz cm7 = 0 cm6 = 0 cm5 = 0 pllcon [4:3] = xx (arbitrary) f ( s y n ) 2 - d i v i d e m o d e f ( ) = 6 . 0 m h z c m 7 = 1 c m 6 = 0 c m 5 = 1 p l l c o n [ 4 : 3 ] = 1 0 cm6 0 1 f( syn ) through mode f( ) = 12.0 mhz cm7 = 1 cm6 = 1 cm5 = 1 pllcon [4:3] = 10 c m 5 1 0 under planning f( syn ) through mode f( ) = 6.0 mhz cm7 = 1 cm6 = 1 cm5 = 1 pllcon [4:3] = 00 f( syn ) through mode f( ) = 8.0 mhz cm7 = 1 cm6 = 1 cm5 = 1 pllcon [4:3] = 01 n o t e : s e t p l l c o n [ 4 : 3 ] = 1 0 b e f o r e s w i t c h i n g t h e s y s t e m c l o c k f r o m x i n t o f s y n . cm5 0 1 cm6 0 1 n o t e : s e t p l l c o n [ 4 : 3 ] = 0 0 b e f o r e s w i t c h i n g t h e s y s t e m c l o c k f r o m x i n t o f s y n . cm5 0 1 cm6 0 1 n o t e : s e t p l l c o n [ 4 : 3 ] = 0 1 b e f o r e s w i t c h i n g t h e s y s t e m c l o c k f r o m x i n t o f s y n . cm5 0 1 c m 5 0 1 n o t e : s e t p l l c o n [ 4 : 3 ] = 0 0 b e f o r e s w i t c h i n g t h e s y s t e m c l o c k f r o m x i n t o f s y n . note : set pllcon [4:3] = 01 before switching the system clock from x in to f syn . fig. 144 state transitions of clock
99 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers table 9 summary of 38k2 groups flash memory version flash memory mode the 38k2 groups flash memory version has an internal new dinor (divided bit line nor) flash memory that can be rewritten with a single power source when v cc is 4.5 to 5.25 v, and 2 power sources when v cc is 3.0 to 4.5 v. for this flash memory, three flash memory modes are available in which to read, program, and erase: the parallel i/o and standard serial i/o modes in which the flash memory can be manipulated using a programmer and the cpu rewrite mode in which the flash memory can be manipulated by the central processing unit (cpu). summary table 9 lists the summary of the 38k2 groups flash memory ver- sion. this flash memory version has some blocks on the flash memory as shown in figure 145 and each block can be erased. the flash memory is divided into user rom area and boot rom area. in addition to the ordinary user rom area to store the mcu op- eration control program, the flash memory has a boot rom area that is used to store a program to control rewriting in cpu rewrite and standard serial i/o modes. this boot rom area has had a standard serial i/o mode control program stored in it when shipped from the factory. however, the user can write a rewrite control program in this area that suits the users application sys- tem. this boot rom area can be rewritten in only parallel i/o mode. item power source voltage (vcc) program/erase v pp voltage (v pp ) flash memory mode erase block division user rom area boot rom area program method erase method program/erase control method number of commands number of program/erase times data retention period rom code protection specifications 3.00 ?5.25 v (program and erase in 4.00 to 5.25 v of vcc.) 3.00 ?4.00 v (program and erase in 3.00 to 5.25 v of vcc.) 4.50 ?5.25 v 3 modes; flash memory can be manipulated as follows: ?pu rewrite mode: manipulated by the central processing unit (cpu). ?arallel i/o mode: manipulated using an external programmer ( note 1 ) ?tandard serial i/o mode: manipulated using an external programmer ( note 1 ) 1 block (32 kbytes) 1 block (4 kbytes) ( note 2 ) byte program batch erasing program/erase control by software command 6 commands 100 times 10 years available in parallel i/o mode and standard serial i/o mode notes 1: in the parallel i/o mode or the standard serial i/o mode, use the exclusive external equipment flash programmer which support s the 38k2 group (flash memory version). 2: the boot rom area has had a standard serial i/o mode control program stored in it when shipped from the factory. this boot rom area can be re- written in only parallel i/o mode.
100 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 145 block diagram of built-in flash memory (1) cpu rewrite mode in cpu rewrite mode, the internal flash memory can be operated on (read, program, or erase) under control of the central process- ing unit (cpu). in cpu rewrite mode, only the user rom area shown in figure 145 can be rewritten; the boot rom area cannot be rewritten. make sure the program and block erase commands are issued for only the user rom area and each block area. the control program for cpu rewrite mode can be stored in either user rom or boot rom area. in the cpu rewrite mode, because the flash memory cannot be read from the cpu, the rewrite con- trol program must be transferred to internal ram area to be executed before it can be executed. microcomputer mode and boot mode the control program for cpu rewrite mode must be written into the user rom or boot rom area in parallel i/o mode beforehand. (if the control program is written into the boot rom area, the stan- dard serial i/o mode becomes unusable.) see figure 145 for details about the boot rom area. normal microcomputer mode is entered when the microcomputer is reset with pulling cnv ss pin low. in this case, the cpu starts operating using the control program in the user rom area. when the microcomputer is reset by pulling the p1 6 (ce ) pin high, the cnv ss pin high, the cpu starts operating using the control program in the boot rom area. this mode is called the ?oot mode. block address block addresses refer to the maximum address of each block. these addresses are used in the block erase command. u s e r r o m a r e a 4 kbytes ffff 16 b o o t r o m a r e a notes 1 : the boot rom area can be rewritten in only parallel i/o mode. (access to any other areas is inhibited.) 2 : to specify a block, use the maximum address in the block. block 1 : 32 kbytes 8000 16 f000 16 ffff 16
101 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers outline performance (cpu rewrite mode) cpu rewrite mode is usable in the single-chip or boot mode. the only user rom area can be rewritten in cpu rewrite mode. in cpu rewrite mode, the cpu erases, programs and reads the in- ternal flash memory as instructed by software commands. this rewrite control program must be transferred to a memory such as the internal ram before it can be executed. the mcu enters cpu rewrite mode by applying 4.50 v to 5.25 v to the cnv ss pin and setting 1 to the cpu rewrite mode select bit (bit 1 of address 0ffe 16 ). software commands are accepted once the mode is entered. use software commands to control program and erase operations. whether a program or erase operation has terminated normally or in error can be verified by reading the status register. figure 146 shows the flash memory control register. bit 0 is the ry/by status flag used exclusively to read the operat- ing status of the flash memory. during programming and erase operations, it is 0 (busy). otherwise, it is 1 (ready). this is equivalent to the ry/by pin function in parallel i/o mode. bit 1 is the cpu rewrite mode select bit. when this bit is set to 1 , the mcu enters cpu rewrite mode. software commands are accepted once the mode is entered. in cpu rewrite mode, the flash memory control register (address 0ffe 16 ) fmcr ( note 1 ) ry/by status flag 0: busy (being written or erased) 1: ready cpu rewrite mode select bit ( note 2 ) 0: normal mode (software commands invalid) 1: cpu rewrite mode (software commands acceptable) cpu rewrite mode entry flag 0: normal mode (software commands invalid) 1: cpu rewrite mode flash memory reset bit ( note 3 ) 0: normal operation 1: reset user area / boot area select bit ( note 4 ) 0: user rom area accessed 1: boot rom area accessed reserved bits (indefinite at read/ 0 at write) b0 b7 n o t e s1 : t h e c o n t e n t s o f f l a s h m e m o r y c o n t r o l r e g i s t e r a r e x x x 0 0 0 0 1 j u s t a f t e r r e s e t r e l e a s e . 2 : f o r t h i s b i t t o b e s e t t o 1 , t h e u s e r n e e d s t o w r i t e 0 a n d t h e n 1 t o i t i n s u c c e s s i o n . i f i t i s n o t t h i s p r o c e d u r e , t h i s b i t w i l l n o t b e s e t t o 1 . a d d i t i o n a l l y , i t i s r e q u i r e d t o e n s u r e t h a t n o i n t e r r u p t w i l l b e g e n e r a t e d d u r i n g t h a t i n t e r v a l . u s e t h e c o n t r o l p r o g r a m i n t h e a r e a e x c e p t t h e b u i l t - i n f l a s h m e m o r y f o r w r i t e t o t h i s b i t . 3 : t h i s b i t i s v a l i d w h e n t h e c p u r e w r i t e m o d e s e l e c t b i t i s 1 . s e t t h i s b i t 3 t o 0 s u b s e q u e n t l y a f t e r s e t t i n g b i t 3 t o 1 . 4 : u s e t h e c o n t r o l p r o g r a m i n t h e a r e a e x c e p t t h e b u i l t - i n f l a s h m e m o r y f o r w r i t e t o t h i s b i t . cpu becomes unable to access the internal flash memory directly. therefore, use the control program in a memory other than inter- nal flash memory for write to bit 1. to set this bit to 1 , it is necessary to write 0 and then write 1 in succession. the bit can be set to 0 by only writing 0 . bit 2 is the cpu rewrite mode entry flag. this flag indicates 1 in cpu rewrite mode, so that reading this flag can check whether cpu rewrite mode has been entered or not. bit 3 is the flash memory reset bit used to reset the control circuit of internal flash memory. this bit is used when exiting cpu rewrite mode and when flash memory access has failed. when the cpu rewrite mode select bit is 1 , setting 1 for this bit resets the control circuit. to set this bit to 1 , it is necessary to write 0 and then write 1 in succession. to release the reset, it is necessary to set this bit to 0 . bit 4 is the user area/boot area select bit. when this bit is set to 1 , boot rom area is accessed, and cpu rewrite mode in boot rom area is available. in boot mode, this bit is set to 1 auto- matically. reprogramming of this bit must be in a memory other than internal flash memory. figure 147 shows a flowchart for setting/releasing cpu rewrite mode. fig. 146 structure of flash memory control register
102 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 147 cpu rewrite mode set/release flowchart end s t a r t e x e c u t e r e a d a r r a y c o m m a n d o r r e s e t f l a s h m e m o r y b y s e t t i n g f l a s h m e m o r y r e s e t b i t ( b y w r i t i n g 1 a n d t h e n 0 i n s u c c e s s i o n ) (note 3) s i n g l e - c h i p m o d e o r b o o t m o d e ( n o t e 1 ) s e t c p u m o d e r e g i s t e r ( n o t e 2 ) using software command execute erase, program, or other operation j u m p t o c o n t r o l p r o g r a m t r a n s f e r r e d i n m e m o r y o t h e r t h a n i n t e r n a l f l a s h m e m o r y ( s u b s e q u e n t o p e r a t i o n s a r e e x e c u t e d b y c o n t r o l p r o g r a m i n t h i s m e m o r y ) t r a n s f e r c p u r e w r i t e m o d e c o n t r o l p r o g r a m t o m e m o r y o t h e r t h a n i n t e r n a l f l a s h m e m o r y notes 1 : when starting the mcu in the single-chip mode or memory expansion mode, supply 4.5 v to 5.25 v to the cnvss pin until checking the cpu rewrite mode entry flag. 2 : set the system clock division ration selection bits of cpu mode register (bits 6 and 7 at address 003b 16 ). 3 : before exiting the cpu rewrite mode after completing erase or program operation, always be sure to execute the read array command or reset the flash memory. write 0 to cpu rewrite mode select bit s e t c p u r e w r i t e m o d e s e l e c t b i t t o 1 ( b y w r i t i n g 0 a n d t h e n 1 i n s u c c e s s i o n ) check cpu rewrite mode entry flag
103 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers notes on cpu rewrite mode take the notes described below when rewriting the flash memory in cpu rewrite mode. operation speed during cpu rewrite mode, set the internal clock to 1.5 mhz or less using the system clock division ratio selection bits (bits 6 and 7 of address 003b 16 ). instructions inhibited against use the instructions which refer to the internal data of the flash memory cannot be used during cpu rewrite mode . interrupts inhibited against use the interrupts cannot be used during cpu rewrite mode because they refer to the internal data of the flash memory. watchdog timer if the watchdog timer has been already activated, internal reset due to an underflow will not occur because the watchdog timer is surely cleared during program or erase. reset reset is always valid. the mcu is activated using the boot mode at release of reset in the condition of cnvss = h , so that the pro- gram will begin at the address which is stored in addresses fffc 16 and fffd 16 of the boot rom area.
104 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers software commands table 10 lists the software commands. after setting the cpu rewrite mode select bit to 1 , write a soft- ware command to specify an erase or program operation. each software command is explained below. read array command (ff 16 ) the read array mode is entered by writing the command code ff 16 in the first bus cycle. when an address to be read is input in one of the bus cycles that follow, the contents of the specified ad- dress are read out at the data bus (d 0 to d 7 ). the read array mode is retained intact until another command is written. read status register command (70 16 ) when the command code 70 16 is written in the first bus cycle, the contents of the status register are read out at the data bus (d 0 to d 7 ) by a read in the second bus cycle. the status register is explained in the next section. clear status register command (50 16 ) this command is used to clear the bits sr4 and sr5 of the status register after they have been set. these bits indicate that opera- tion has ended in an error. to use this command, write the command code 50 16 in the first bus cycle. program command (40 16 ) program operation starts when the command code 40 16 is writ- ten in the first bus cycle. then, if the address and data to program are written in the 2nd bus cycle, the control circuit of flash memory (data programming and verification) will start a program. whether the write operation is completed can be confirmed by _____ reading the status register or the ry/by status flag. when the program starts, the read status register mode is entered automati- cally and the contents of the status register is read at the data bus (db 0 to db 7 ). the status register bit 7 (sr7) is set to 0 at the same time the write operation starts and is returned to 1 upon completion of the write operation. in this case, the read status reg- ister mode remains active until the read array command (ff 16 ) is written. table 10 list of software commands (cpu rewrite mode) ____ during the program movement, the ry/by status flag of flash memory control register is set to 0 . when the program com- pletes, it becomes 1 . at program end, program results can be checked by reading the status register. fig. 148 program flowchart command p r o g r a m c l e a r s t a t u s r e g i s t e r r e a d a r r a y r e a d s t a t u s r e g i s t e r x x f i r s t b u s c y c l e second bus cycle f f 1 6 7 0 1 6 5 0 1 6 4 0 1 6 write write write write xs r d read w r i t e e r a s e a l l b l o c k s2 0 1 6 write x 20 16 w r i t e (note 1) w a ( n o t e 2 ) wd (note 2) block erase 2 0 1 6 write d0 16 w r i t eb a (note 3) mode address mode a d d r e s s data (d 0 to d 7 ) ( d 0 t o d 7 ) (note 4) n o t e s 1 : srd = status register data 2: wa = write address, wd = write data 3: ba = block address to be erased (input the maximum address of each block.) 4: x denotes a given address in the user rom area . c y c l e n u m b e r 1 2 1 2 2 2 x x x x data s t a r t w r i t e 4 0 1 6 s t a t u s r e g i s t e r r e a d program completed n o y e s w r i t e a d d r e s s w r i t e d a t a sr4 = 0 ? program error no y e s s r 7 = 1 ? o r r y / b y = 1 ? w r i t e
105 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers erase all blocks command (20 16 /20 16 ) by writing the command code 20 16 in the first bus cycle and the confirmation command code 20 16 in the second bus cycle that follows, the operation of erase all blocks (erase and erase verify) starts. whether the erase all blocks command is terminated can be con- ____ firmed by reading the status register or the ry/by status flag of flash memory control register. when the erase all blocks operation starts, the read status register mode is entered automatically and the contents of the status register can be read out at the data bus (d 0 to d 7 ). the status register bit 7 (sr7) is set to 0 at the same time the erase operation starts and is returned to 1 upon comple- tion of the erase operation. in this case, the read status register mode remains active until the read array command (ff 16 ) is writ- ten. ____ the ry/by status flag is 0 during erase operation and 1 when the erase operation is completed as is the status register bit 7. after the erase all blocks end, erase results can be checked by reading the status register. for details, refer to the section where the status register is detailed. block erase command (20 16 /d0 16 ) by writing the command code 20 16 in the first bus cycle and the confirmation command code d0 16 and the block address in the second bus cycle that follows, the block erase (erase and erase verify) operation starts for the block address of the flash memory to be specified. whether the block erase operation is completed can be confirmed ____ by reading the status register or the ry/by status flag of flash memory control register. at the same time the block erase opera- tion starts, the read status register mode is automatically entered, so that the contents of the status register can be read out. the status register bit 7 (sr7) is set to 0 at the same time the block erase operation starts and is returned to 1 upon completion of the block erase operation. in this case, the read status register mode remains active until the read array command (ff 16 ) is writ- ten. ____ the ry/by status flag is 0 during block erase operation and 1 when the block erase operation is completed as is the status reg- ister bit 7. after the block erase ends, erase results can be checked by read- ing the status register. for details, refer to the section where the status register is detailed. w r i t e 2 0 1 6 2 0 1 6 / d 0 1 6 b l o c k a d d r e s s erase completed n o y e s s t a r t write sr5 = 0 ? e r a s e e r r o r yes n o 2 0 1 6 : e r a s e a l l b l o c k s d 0 1 6 : b l o c k e r a s e sr 7 = 1 ? or ry/by = 1 ? s t a t u s r e g i s t e r r e a d fig. 149 erase flowchart
106 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers table 11 definition of each bit in status register status register (srd) the status register shows the operating status of the flash memory and whether erase operations and programs ended suc- cessfully or in error. it can be read in the following ways: (1) by reading an arbitrary address from the user rom area after writing the read status register command (70 16 ) (2) by reading an arbitrary address from the user rom area in the period from when the program starts or erase operation starts to when the read array command (ff 16 ) is input. also, the status register can be cleared by writing the clear status register command (50 16 ). after reset, the status register is set to 80 16 . table 11 shows the status register. each bit in this register is ex- plained below. sequencer status (sr7) the sequencer status indicates the operating status of the flash memory. this bit is set to 0 (busy) during write or erase operation and is set to 1 when these operations ends. after power-on, the sequencer status is set to 1 (ready). erase status (sr5) the erase status indicates the operating status of erase operation. if an erase error occurs, it is set to 1 . when the erase status is cleared, it is set to 0 . program status (sr4) the program status indicates the operating status of write opera- tion. when a write error occurs, it is set to 1 . the program status is set to 0 when it is cleared. if 1 is written for any of the sr5 and sr4 bits, the program, erase all blocks, and block erase commands are not accepted. before executing these commands, execute the clear status regis- ter command (50 16 ) and clear the status register. each bit of srd0 bits sr7 (bit7) sr6 (bit6) sr5 (bit5) sr4 (bit4) sr3 (bit3) sr2 (bit2) sr1 (bit1) sr0 (bit0) definition 1 0 sequencer status reserved erase status program status reserved reserved reserved reserved ready - terminated in error terminated in error - - - - status name busy - terminated normally terminated normally - - - -
107 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers full status check by performing full status check, it is possible to know the execu- tion results of erase and program operations. figure 150 shows a full status check flowchart and the action to be taken when each error occurs. fig. 150 full status check flowchart and remedial procedure for errors read status register s r 4 = 1 a n d s r5 = 1 ? n o y e s s r 5 = 0 ? y e s erase error n o s r 4 = 0 ? yes n o c o m m a n d s e q u e n c e e r r o r p r o g r a m e r r o r e n d ( b l o c k e r a s e , p r o g r a m ) execute the clear status register command (50 16 ) to clear the status register. try performing the operation one more time after confirming that the command is entered correctly. should an erase error occur, the block in error cannot be used. note : when one of sr5 and sr4 is set to 1 , none of the program, erase all blocks, and block erase commands is accepted. execute the clear status register command (50 16 ) before executing these commands. should a program error occur, the block in error cannot be used.
108 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers functions to inhibit rewriting flash memory version to prevent the contents of internal flash memory from being read out or rewritten easily, this mcu incorporates a rom code protect function for use in parallel i/o mode and an id code check func- tion for use in standard serial i/o mode. rom code protect function the rom code protect function is the function to inhibit reading out or modifying the contents of internal flash memory by using the rom code protect control register (address ffdb 16 ) in paral- lel i/o mode. figure 151 shows the rom code protect control register (address ffdb 16 ). (this address exists in the user rom area.) if one or both of the pair of rom code protect bits is set to 0 , the rom code protect is turned on, so that the contents of internal flash memory are protected against readout and modification. the rom code protect is implemented in two levels. if level 2 is se- lected, the flash memory is protected even against readout by a shipment inspection lsi tester, etc. when an attempt is made to select both level 1 and level 2, level 2 is selected by default. if both of the two rom code protect reset bits are set to 00 , the rom code protect is turned off, so that the contents of internal flash memory can be read out or modified. once the rom code protect is turned on, the contents of the rom code protect reset bits cannot be modified in parallel i/o mode. use the serial i/o or cpu rewrite mode to rewrite the contents of the rom code pro- tect reset bits. fig. 151 structure of rom code protect control register r o m c o d e p r o t e c t c o n t r o l r e g i s t e r ( a d d r e s s f f d b 1 6 ) r o m c p reserved bits ( 1 at read/write) rom code protect level 2 set bits (romcp2) ( notes 1, 2 ) b3b2 0 0: protect enabled 0 1: protect enabled 1 0: protect enabled 1 1: protect disabled rom code protect reset bits ( note 3 ) b5b4 0 0: protect removed 0 1: protect set bits effective 1 0: protect set bits effective 1 1: protect set bits effective rom code protect level 1 set bits (romcp1) ( note 1 ) b7b6 0 0: protect enabled 0 1: protect enabled 1 0: protect enabled 1 1: protect disabled b 0 b 7 notes 1 : when rom code protect is turned on, the internal flash memory is protected against readout or modification in parallel i/o mode. 2 : when rom code protect level 2 is turned on, rom code readout by a shipment inspection lsi tester, etc. also is inhibited. 3 : the rom code protect reset bits can be used to turn off rom code protect level 1 and rom code protect level 2. however, since these bits cannot be modified in parallel i/o mode, they need to be rewritten in serial i/o mode or cpu rewrite mode.
109 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers id code check function use this function in standard serial i/o mode. when the contents of the flash memory are not blank, the id code sent from the pro- grammer is compared with the id code written in the flash memory to see if they match. if the id codes do not match, the commands sent from the programmer are not accepted. the id code consists of 8-bit data, and its areas are ffd4 16 to ffda 16 . write a pro- gram which has had the id code preset at these addresses to the flash memory. fig. 152 id code store addresses rom cord protect control id7 id6 id5 id4 id3 id2 id1 ffdb 16 ffda 16 ffd9 16 ffd8 16 ffd7 16 ffd6 16 ffd5 16 ffd4 16 address interrupt vector area
110 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers (2) parallel i/o mode parallel i/o mode is the mode which parallel output and input soft- ware command, address, and data required for the operations (read, program, erase, etc.) to a built-in flash memory. use the ex- clusive external equipment flash programmer which supports the 38k2 group (flash memory version). refer to each programmer maker s handling manual for the details of the usage. user rom and boot rom areas in parallel i/o mode, the user rom and boot rom areas shown in fig- ure 145 can be rewritten. both areas of flash memory can be operated on in the same way. the boot rom area is 4 kbytes in size. it is located at addresses f000 16 through ffff 16 . make sure program and block erase opera- tions are always performed within this address range. (access to any location outside this address range is prohibited.) in the boot rom area, an erase block operation is applied to only one 4 kbyte block. the boot rom area has had a standard serial i/o mode control pro- gram stored in it when shipped from the mitsubishi factory. there- fore, using the device in standard serial i/o mode, you must perform program and block erase in the user rom area.
111 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers (3) standard serial i/o mode the standard serial i/o mode inputs and outputs the software commands, addresses and data needed to operate (read, pro- gram, erase, etc.) the internal flash memory. this i/o is clock synchronized serial. this mode requires a purpose-specific pe- ripheral unit.the standard serial i/o mode is different from the parallel i/o mode in that the cpu controls flash memory rewrite (uses the cpu rewrite mode), rewrite data input and so forth. the standard serial i/o mode is started by connecting ??to the p1 6 (ce) pin and ??to the p4 2 (s clk ) pin and ??to the cnv ss (v pp ) pin (apply 4.5 v to 5.25 v to vpp from an external source), and re- leasing the reset operation. (in the ordinary microcomputer mode, set cnvss pin to ??level.) this control program is written in the boot rom area when the product is shipped from mitsubishi. accordingly, make note of the fact that the standard serial i/o mode cannot be used if the boot rom area is rewritten in parallel i/o mode. figure 153 shows the pin connections for the standard serial i/o mode. in standard serial i/o mode, serial data i/o uses the four serial i/o pins s clk , rxd, txd and s rdy (busy). the s clk pin is the trans- fer clock input pin through which an external transfer clock is input. the txd pin is for cmos output. the s rdy (busy) pin out- puts ??level when ready for reception and ??level when reception starts. serial data i/o is transferred serially in 8-bit units. in standard serial i/o mode, only the user rom area shown in figure 145 can be rewritten. the boot rom area cannot. in standard serial i/o mode, a 7-byte id code is used. when there is data in the flash memory, commands sent from the peripheral unit (programmer) are not accepted unless the id code matches. outline performance (standard serial i/o mode) in standard serial i/o mode, software commands, addresses and data are input and output between the mcu and peripheral units (serial programer, etc.) using 4-wire clock-synchronized serial i/o. in reception, software commands, addresses and program data are synchronized with the rise of the transfer clock that is input to the s clk pin, and are then input to the mcu via the rxd pin. in transmission, the read data and status are synchronized with the fall of the transfer clock, and output from the txd pin. the txd pin is for cmos output. transfer is in 8-bit units with lsb first. when busy, such as during transmission, reception, erasing or program execution, the s rdy (busy) pin is ??level. accordingly, always start the next transfer after the s rdy (busy) pin is ? level. also, data and status registers in a memory can be read after in- putting software commands. status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. here following explains software commands, status registers, etc.
112 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers table 12 description of pin function (standard serial i/o mode) pin name signal name i/o v cc ,v ss power supply v cc e power supply cnv ss v pp i cnv ss 2 cnv ss 2i v ref analog reference voltage i dv cc , pv cc analog power supply pv ss analog power supply reset reset input i x in clock input i x out clock output o usbv ref usb reference voltage input i tron usb reference voltage output o d0+,d0- usb upstream input i/o d1+,d1- usb downstream input i/o d2+,d2- usb downstream input i/o p0 0 to p0 7 input port p0 i p1 0 to p1 5 input port p1 i p1 6 input port p1 i p1 7 input port p1 i p2 0 to p2 4 input port p2 i p3 0 to p3 7 input port p3 i p4 0 rxd input i p4 1 txd output o p4 2 s clk input i p4 3 busy output o p5 0 to p5 7 input port p5 i p6 0 to p6 3 input port p6 i function apply 3.00 to 5.25 v to the vcc pin and 0 v to the vss pin. connect this pin to vcc. connect this pin to v pp (v pp = 4.50 to 5.25 v). connect this pin to vss. connect this pin to vcc when not using. connect this pin to vcc. connect this pin to vss. to reset, input ??level for 20 cycles or longer clocks of . connect a ceramic or crystal resonator between the x in and x out pins. when entering an externally drived clock, enter it from x in and leave x out open. connect this pin to vcc when not using. leave this pin open when not using. input ??level when not using. input ??level when not using. input ??level when not using. input ??or ??level, or keep open. input ??or ??level, or keep open. input ??or ??level, or keep open.input ??level only at release of reset. input ??or ??level, or keep open. input ??or ??level, or keep open. input ??or ??level, or keep open. this is a serial data input pin. this is a serial data output pin. this is a serial clock input pin.input ??level only at release of reset. this is a busy output pin. input ??or ??level, or keep open. input ??or ??level, or keep open.
113 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 153 pin connection diagram in standard serial i/o mode p 0 6 1 2 3 4 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 5 6 17 18 19 2 0 21 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 62 63 64 p 1 2 / d q 2 / a n 2 p 1 5 / d q 5 / a n 5 c n v s s c n v s s 2 p 6 0 ( l e d 0 ) p 6 1 ( l e d 1 ) p 6 2 ( l e d 2 ) v c c v s s x i n x o u t p 6 3 ( l e d 3 ) p v s s d 2 + p 2 4 m 3 8 k 2 9 f 8 f p / h p p 1 3 / d q 3 / a n 3 p 1 4 / d q 4 / a n 4 4 5 4 6 4 7 4 8 p v c c d v c c u s b v r e f tron d 0 + d 0 - d 1 - d1+ d 2 - p 2 5 p 2 6 p 2 7 p 5 0 / i n t 0 p 5 1 / c n t r 0 p 5 2 / i n t 1 p 5 3 p 5 4 p 5 5 p 5 6 p 5 7 p 0 0 p 0 1 p 0 2 p 0 3 p 0 4 p 0 5 p 0 7 p 4 0 / e x d r e q / r x d p 4 1 / e x d a c k / t x d p 4 2 / e x t c / s c l k p 4 3 / e x a 1 / s r d y p 3 0 p 3 1 p 3 2 p 3 3 / e x i n t p3 4 /e x cs p 3 5 / e x w r p3 6 /e x rd p 3 7 / e x a 0 p 1 0 / d q 0 / a n 0 p1 1 /dq 1 /an 1 r e s e t p 1 6 / d q 6 / a n 6 p 1 7 / d q 7 / a n 7 v c c e v r e f v p p vcc vss t x d b u s y r x d s c l k r e s e t m o d e s e t u p m e t h o d signal value c o n n e c t t o o s c i l l a t o r c i r c u i t . p a c k a g e o u t l i n e : 6 4 p 6 u - a , 6 4 p 6 q - a cnvss 4.5 to 5.25 v s clk vcc ( note 2 ) reset vss vcc ce vcc ( note 2 ) ( n o t e 1 ) n o t e s 1 : c o n n e c t t o v c c i n t h e c a s e o f v c c = 4 . 5 v t o 5 . 2 5 v . c o n n e c t t o v p p ( = 4 . 5 v t o 5 . 2 5 v ) i n t h e c a s e o f v c c = 4 . 0 v t o 4 . 5 v . 2 : s u p p l y v c c a t r e l e a s i m g r e s e t . c e
114 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers software commands table 13 lists software commands. in standard serial i/o mode, erase, program and read are controlled by transferring software commands via the rxd pin. software commands are explained 2nd byte address (middle) 3rd byte address (high) 4th byte data output 5th byte data output 6th byte data output ..... data output to 259th byte data input to 259th byte ff 16 when id is not verified not acceptable 1st byte transfer notes1: shading indicates transfer from the internal flash memory microcomputer to a programmer. all other data is transferred from a programmer to the in- ternal flash memory microcomputer. 2: srd refers to status register data. srd1 refers to status register 1 data. 3: all commands can be accepted when the flash memory is totally blank. 4: address low is a 0 to a 7 ; address middle is a 8 to a 15 ; address high is a 16 to a 23 . address-high a 16 to a 23 are always 00 16 . here below. basically, the software commands of the standard se- rial i/o mode are the same as that of the parallel i/o mode, but the block erase function is excluded, and 4 commands are added: id check, download, version data output and boot rom area output functions. table 13 software commands (standard serial i/o mode) control command 1 page read 2 page program 41 16 address (middle) address (high) data input data input data input not acceptable not acceptable acceptable 3 erase all blocks a7 16 d0 16 srd1 output 4 read status register 70 16 srd output 5 clear status register 50 16 address (low) address (middle) not acceptable 6 id check function f5 16 acceptable 7 download function fa 16 size (low) size (high) address (high) check- sum id size id1 to id7 not acceptable 8 version data output function fb 16 data input to required number of times acceptable fc 16 version data output address (high) version data output data output version data output data output version data output data output version data output to 9th byte data output to 259th byte not acceptable 9 boot rom area output function version data output address (middle)
115 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers read status register command this command reads status information. when the 70 16 com- mand code is transferred with the 1st byte, the contents of the status register (srd) with the 2nd byte and the contents of status register 1 (srd1) with the 3rd byte are read. the contents of software commands are explained as follows. page read command this command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. execute the page read command as explained here following. (1) transfer the ff 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) from the 4th byte onward, data (d 0 to d 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 will be output se- quentially from the smallest address first synchronized with the fall of the clock. data0 data255 a 8 t o a 1 5 a 16 to a 23 f f 1 6 s c l k r x d t x d s r d y ( b u s y ) s r d o u t p u t s r d 1 o u t p u t s c l k r x d t x d s r d y ( b u s y ) 70 16 fig. 154 timing for page read fig. 155 timing for reading status register
116 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 156 timing for clear status register clear status register command this command clears the bits (sr3 to sr5) which are set when the status register operation ends in error. when the 50 16 com- mand code is sent with the 1st byte, the aforementioned bits are cleared. when the clear status register operation ends, the s rdy (busy) signal changes from h to l level. s c l k r x d t x d s r d y ( b u s y ) 50 16 a 8 t o a 1 5 a 1 6 t o a 2 3 4 1 1 6 d a t a 0 d a t a 2 5 5 s c l k r x d t x d s r d y ( b u s y ) page program command this command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. execute the page pro- gram command as explained here following. (1) transfer the 41 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) from the 4th byte onward, as write data (d 0 to d 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 is input sequentially from the smallest address first, that page is auto- matically written. when reception setup for the next 256 bytes ends, the s rdy (busy) signal changes from h to l level. the result of the page program can be known by reading the status register. for more information, see the section on the status register. fig. 157 timing for page program
117 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers erase all blocks command this command erases the contents of all blocks. execute the erase all blocks command as explained here following. (1) transfer the a7 16 command code with the 1st byte. (2) transfer the verify command code d0 16 with the 2nd byte. with the verify command code, the erase operation will start and continue for all blocks in the flash memory. when erase all blocks end, the s rdy (busy) signal changes from h to l level. the result of the erase operation can be known by reading the status register. a7 16 d 0 1 6 s c l k r x d t x d s r d y ( b u s y ) fig. 158 timing for erase all blocks
118 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers download command this command downloads a program to the ram for execution. execute the download command as explained here following. (1) transfer the fa 16 command code with the 1st byte. (2) transfer the program size with the 2nd and 3rd bytes. (3) transfer the check sum with the 4th byte. the check sum is added to all data sent with the 5th byte onward. (4) the program to execute is sent with the 5th byte onward. when all data has been transmitted, if the check sum matches, the downloaded program is executed. the size of the program will vary according to the internal ram. fig. 159 timing for download f a 1 6 p r o g r a m d a t a program data data size (low) check sum s clk rxd txd s rdy (busy) d a t a s i z e ( h i g h )
119 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers version information output command this command outputs the version information of the control pro- gram stored in the boot rom area. execute the version information output command as explained here following. (1) transfer the fb 16 command code with the 1st byte. (2) the version information will be output from the 2nd byte on- ward. this data is composed of 8 ascii code characters. fig. 160 timing for version information output fb 16 x v e r s clk rxd txd s rdy (busy) boot rom area output command this command reads the control program stored in the boot rom area in page (256 bytes) unit. execute the boot rom area output command as explained here following. (1) transfer the fc 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) from the 4th byte onward, data (d 0 to d 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 will be output se- quentially from the smallest address first synchronized with the fall of the clock. fig. 161 timing for boot rom area output f c 1 6 a 8 t o a 1 5 a 1 6 t o a 2 3 d a t a 0d a t a 2 5 5 s cl k rx d tx d s rdy (busy)
120 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers id check this command checks the id code. execute the boot id check command as explained here following. id code when the flash memory is not blank, the id code sent from the se- rial programmer and the id code written in the flash memory are compared to see if they match. if the codes do not match, the command sent from the serial programmer is not accepted. an id code contains 8 bits of data. area is, from the 1st byte, addresses ffd4 16 to ffda 16 . write a program into the flash memory, which already has the id code set for these addresses. fig. 162 timing for id check id size i d 1 id7 f 5 1 6 d4 16 f f 1 6 0 0 1 6 s clk rxd txd s rdy (busy) r o m c o d e p r o t e c t c o n t r o l i d 7 i d 6 i d 5 i d 4 id3 i d 2 i d 1 f f d b 1 6 f f d a 1 6 f f d 9 1 6 ffd8 16 ffd7 16 ffd6 16 f f d 5 1 6 f f d 4 1 6 a d d r e s s interrupt vector area fig. 163 id code storage addresses (1) transfer the f5 16 command code with the 1st byte. (2) transfer addresses a 0 to a 7 , a 8 to a 15 and a 16 to a 23 ( 00 16 ) of the 1st byte of the id code with the 2nd, 3rd and 4th respec- tively. (3) transfer the number of data sets of the id code with the 5th byte. (4) transfer the id code with the 6th byte onward, starting with the 1st byte of the code.
121 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers status register (srd) the status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. it can be read by writing the read status register command (70 16 ). also, the status register is cleared by writing the clear status register command (50 16 ). table 14 lists the definition of each status register bit. after releas- ing the reset, the status register becomes 80 16 . sequencer status (sr7) the sequencer status indicates the operating status of the the flash memory. after power-on and recover from deep power down mode, the se- quencer status is set to 1 (ready). this status bit is set to 0 (busy) during write or erase operation and is set to 1 upon completion of these operations. erase status (sr5) the erase status indicates the operating status of erase operation. if an erase error occurs, it is set to 1 . when the erase status is cleared, it is set to 0 . program status (sr4) the program status indicates the operating status of write opera- tion. if a write error occurs, it is set to 1 . when the program status is cleared, it is set to 0 . srd0 bits sr7 (bit7) sr6 (bit6) sr5 (bit5) sr4 (bit4) sr3 (bit3) sr2 (bit2) sr1 (bit1) sr0 (bit0) definition 1 0 table 14 status register (srd) status name sequencer status reserved erase status program status reserved reserved reserved reserved ready - terminated in error terminated in error - - - - busy - terminated normally terminated normally - - - -
122 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers status register 1 (srd1) the status register 1 indicates the status of serial communica- tions, results from id checks and results from check sum comparisons. it can be read after the srd by writing the read sta- tus register command (70 16 ). also, status register 1 is cleared by writing the clear status register command (50 16 ). table 15 lists the definition of each status register 1 bit. this regis- ter becomes 00 16 when power is turned on and the flag status is maintained even after the reset. table 15 status register 1 (srd1) 00 not verified 01 verification mismatch 10 reserved 11 verified sr15 (bit7) sr14 (bit6) sr13 (bit5) sr12 (bit4) sr11 (bit3) sr10 (bit2) sr9 (bit1) sr8 (bit0) boot update completed bit reserved reserved checksum match bit id check completed bits data reception time out reserved 1 update completed - - match time out - 0 not update - - mismatch normal operation - definition srd1 bits status name boot update completed bit (sr15) this flag indicates whether the control program was downloaded to the ram or not, using the download function. check sum consistency bit (sr12) this flag indicates whether the check sum matches or not when a program, is downloaded for execution using the download func- tion. id check completed bits (sr11 and sr10) these flags indicate the result of id checks. some commands cannot be accepted without an id check. data reception time out (sr9) this flag indicates when a time out error is generated during data reception. if this flag is attached during data reception, the re- ceived data is discarded and the mcu returns to the command wait state.
123 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers full status check results from executed erase and program operations can be known by running a full status check. figure 164 shows a flow- chart of the full status check and explains how to remedy errors which occur. r e a d s t a t u s r e g i s t e r s r 4 = 1 a n d s r5 = 1 ? n o y e s s r 5 = 0 ? y e s erase error n o s r 4 = 0 ? y e s no c o m m a n d s e q u e n c e e r r o r program error e n d ( e r a s e , p r o g r a m ) execute the clear status register command (50 16 ) to clear the status register. try performing the operation one more time after confirming that the command is entered correctly. should an erase error occur, the block in error cannot be used. note : when one of sr5 to sr4 is set to 1 , none of the program, erase all blocks, and block erase commands is accepted. execute the clear status register command (50 16 ) before executing these commands. should a program error occur, the block in error cannot be used. fig. 164 full status check flowchart and remedial procedure for errors
124 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers example circuit application for standard serial i/o mode figure 165 shows a circuit application for the standard serial i/o mode. control pins will vary according to a programmer, therefore see a programmer manual for more information. s rdy (busy) s cl k rxd txd cnvss c l o c k i n p u t b u s y o u t p u t d a t a i n p u t d a t a o u t p u t m 3 8 k 2 9 f 8 n o t e s 1 : c o n t r o l p i n s a n d e x t e r n a l c i r c u i t r y w i l l v a r y a c c o r d i n g t o a p r o g r a m m e r . f o r m o r e i n f o r m a t i o n , s e e t h e p r o g r a m m e r m a n u a l . 2 : i n t h i s e x a m p l e , t h e v p p p o w e r s u p p l y i s s u p p l i e d f r o m a n e x t e r n a l s o u r c e ( p r o g r a m m e r ) . t o u s e t h e u s e r s p o w e r s o u r c e , c o n n e c t t o 4 . 5 v t o 5 . 2 5 v . v p p p o w e r s o u r c e i n p u t v c c v c c p1 6 (ce) fig. 165 example circuit application for standard serial i/o mode
125 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers notes on programming processor status register the contents of the processor status register (ps) after a reset are undefined, except for the interrupt disable flag (i) which is 1. af- ter a reset, initialize flags which affect program execution. in particular, it is essential to initialize the index x mode (t) and the decimal mode (d) flags because of their effect on calculations. interrupts the contents of the interrupt request bits do not change immedi- ately after they have been written. after writing to an interrupt request register, execute at least one instruction before perform- ing a bbc or bbs instruction. decimal calculations to calculate in decimal notation, set the decimal mode flag (d) to 1 , then execute an adc or sbc instruction. after executing an adc or sbc instruction, execute at least one instruction be- fore executing a sec, clc, or cld instruction. in decimal mode, the values of the negative (n), overflow (v), and zero (z) flags are invalid. timers when n (0 to 255) is written to a timer latch, the frequency divi- sion ratio is 1/(n+1). when a count source of timer x is switched, stop a count of timer x. multiplication and division instructions the index x mode (t) and the decimal mode (d) flags do not af- fect the mul and div instruction. the execution of these instructions does not change the con- tents of the processor status register. ports the contents of the port direction registers cannot be read. the following cannot be used: the data transfer instruction (lda, etc.) the operation instruction when the index x mode flag (t) is 1 the addressing mode which uses the value of a direction regis- ter as an index the bit-test instruction (bbc or bbs, etc.) to a direction register the read-modify-write instructions (ror, clb, or seb, etc.) to a direction register. use instructions such as ldm and sta, etc., to set the port direc- tion registers. a-d converter the comparator uses capacitive coupling amplifier whose charge will be lost if the clock frequency is too low. therefore, make sure that f(system clock) in the middle/high- speed mode is at least on 500 khz during an a-d conversion. do not execute the stp or wit instruction during an a-d conver- sion. instruction execution time the instruction execution time is obtained by multiplying the fre- quency of the internal clock by the number of cycles needed to execute an instruction. however, when using the usb function or exb function, an occurrence of one-wait due to the multichannel ram will double an internal clock cycle.
126 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers definition of a-d conversion accuracy the a-d conversion accuracy is defined below (refer to figure 166). relative accuracy ? zero transition voltage (v ot ) this means an analog input voltage when the actual a-d con- version output data changes from 0 to 1. ? full-scale transition voltage (v fst ) this means an analog input voltage when the actual a-d con- version output data changes from 1023 to 1022. ? non-linearity error this means a deviation from the line between v ot and v fst of a converted value between v ot and v fst . ? differential non-linearity error this means a deviation from the input potential difference re- quired to change a converted value between v ot and v fst by 1 lsb of the 1 lsb at the relative accuracy. absolute accuracy this means a deviation from the ideal characteristics between 0 to v ref of actual a-d conversion characteristics. v ref 1024 vn: analog input voltage when the output data changes from n to n + 1 (n = 0 to 1022) 1 lsb at relative accuracy (v) 1 lsb at absolute accuracy (v) v fst v ot 1022 analog voltage v ref v 1022 v n v 1 v 0 zero transition voltage (v 0t ) full-scale transition voltage (v fst ) non-linearity error= actual a-d conversion characteristics v n+1 n+1 n 1022 1023 1 0 ideal line of a-d conversion between v 0 to v 1022 output data b a a: 1lsb at relative accuracy b: v n+1 -v n c: difference between the ideal vn and actual vn differential non-linearity error= b-a a [lsb] c c a [lsb] fig. 166 definition of a-d conversion accuracy
127 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers notes on usage handling of power source pin in order to avoid a latch-up occurrence, connect a capacitor suit- able for high frequencies as bypass capacitor between power source pin (vcc pin) and gnd pin (vss pin). besides, connect the capacitor to as close as possible. for bypass capacitor which should not be located too far from the pins to be connected, a ce- ramic or electrolytic capacitor of 1.0 f is recommended. usb port pins (d0+, d0-, d1+, d1-, d2+, d2-) treatment the usb specification requires a driver-impedance 28 to 44 ?. in order to meet the usb specification impedance requirements, connect a resistor (27 ? recommended) in series to the usb port pins. in addition, in order to reduce the ringing and control the falling/ rising timing and a crossover point, connect a capacitor between the usb port pins and the vss pin if necessary. the values and structure of those peripheral elements depend on the impedance characteristics and the layout of the printed circuit board. accordingly, evaluate your system and observe waveforms before actual use and decide use of elements and the values of resistors and capacitors. make sure the usb d+/d- lines do not cross any other wires. keep a large gnd area to protect the usb lines. also, make sure you use a usb specification compliant connecter for the connec- tion. usbv ref pin treatment (noise elimination) connect a capacitor between the usbv ref pin and the vss pin. the capacitor should have a 2.2 f capacitor (electrolytic capaci- tor) and a 0.1 f capacitor (ceramic type capacitor) connected in parallel. in vcc = 3.0 to 3.6 v operation, connect the usbv ref pin directly to the vcc pin in order to supply power to the usb port circuit. in addition, you will need to disable the built-in usb reference volt- age circuit in this operation (set bit 4 of the usb control register to 0 .) if you are using the bus powered supply in this condition, the dc-dc converter must be placed outside the mcu. in vcc = 4.00 to 5.25 v operation, do not connect the external dc-dc converter to the usbv ref pin. use the built-in usb refer- ence voltage circuit. flash memory version the cnvss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (v pp pin) as well. to improve the noise reduction, connect a track between cnvss pin and vss pin or vcc pin with 1 to 10 k ? resistance. the mask rom version track of cnvss pin has no operational in- terference even if it is connected to vss pin or vcc pin via a resistor. electric characteristic differences between mask rom and flash memory version mcus there are differences in electric characteristics, operation margin, noise immunity, and noise radiation between mask rom and flash memory version mcus due to the difference in the manufac- turing processes. when manufacturing an application system with the flash memory version and then switching to use of the mask rom ver- sion, please perform sufficient evaluations for the commercial samples of the mask rom version. data required for mask orders the following are necessary when ordering a mask rom produc- tion: 1. mask rom order confirmation form ? 2. mark specification form ? 3. data to be written to rom, in eprom form (three identical cop- ies) or one floppy disk. ? mask rom confirmation forms/mark specification forms http://www.infomicom.maec.co.jp/
128 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers ?.3 to 6.5 ?.3 to v cc + 0.3 ?.3 to v cc + 0.3 ?.3 to v cc + 0.3 ?.3 to v cc + 0.3 ?.3 to 6.5 ?.5 to 3.8 ?.3 to v cc + 0.3 ?.5 to 3.8 500 ?0 to 85 25? ?0 to 125 power source voltage analog power source voltage v cc e, v ref , pv cc , dv cc , usbv ref input voltage p0 0 ?0 7 , p1 0 ?1 7 , p2 4 ?2 7 , p3 0 p3 7 , p4 0 ?4 3 , p5 0 ?5 7 , p6 0 ?6 3 input voltage reset, x in , cnv ss2 input voltage cnv ss mask rom version flash memory version input voltage d0+, d0-, d1+, d1-, d2+, d2- output voltage p0 0 ?0 7 , p1 0 ?1 7 , p2 4 ?2 7 , p3 0 p3 7 , p4 0 ?4 3 , p5 0 ?5 7 , p6 0 ?6 3 , x out output voltage d0+, d0-, d1+, d1-, d2+, d2-, tron power dissipation ( note ) operating temperature storage temperature v v v v v v v v v mw ? ? ? v cc av cc v i v i v i v i v o v o p d t opr t stg conditions symbol ratings unit parameter all voltages are based on v ss . output transistors are cut off. ta = 25? note: the maximum rating value depends on not only the mcu? power dissipation but the heat consumption characteristics of the packa ge. electrical characteristics absolute maximum ratings table 16 absolute maximum ratings mcu operating in flash memory mode (for flash memory ver- sion)
129 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers table 17 recommended operating conditions (vcc = 3.00 to 5.25 v, vss = 0 v, ta = ?0 to 85?, unless otherwise noted) recommended operating conditions symbol parameter unit limits v cc av cc av cc v ref v ref v ss av ss v ih v ih v ih v ih v il v il v il v il v v v v v v v v v v v v v v v v v v v 5.25 5.25 5.25 v cc 3.6 v cc v cc v cc e v cc 3.6 0.2v cc 0.2v cc e 0.2v cc 0.8 max. power source voltage v cc system clock 12 mhz (2-/4-/8-divide mode) system clock 8 mhz system clock 6 mhz analog power source voltage pv cc , dv cc analog power source voltage v cc e analog reference voltage v ref analog reference voltage usbv ref vcc = 3.6 to 4.0 v vcc = 3.0 to 3.6 v power source voltage v ss analog power source voltage pv ss ??input voltage p0 0 ?0 7 , p2 4 ?2 7 , p5 0 ?5 7 , p6 0 ?6 3 ??input voltage p1 0 ?1 7 , p3 0 ?3 7 , p4 0 ?4 3 ??input voltage reset, x in , cnv ss , cnv ss2 ??input voltage d0+, d0-, d1+, d1-, d2+, d2- ??input voltage p0 0 ?0 7 , p2 4 ?2 7 , p5 0 ?5 7 , p6 0 ?6 3 ??input voltage p1 0 ?1 7 , p3 0 ?3 7 , p4 0 ?4 3 ??input voltage reset, x in , cnv ss , cnv ss2 ??input voltage d0+, d0-, d1+, d1-, d2+, d2- typ. 5.00 5.00 5.00 v cc v cc 0 0 4.00 4.00 3.00 2.0 3.0 3.0 0.8v cc 0.8v cc e 0.8v cc 2.0 0 0 0 0 min.
130 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers table 18 recommended operating conditions (vcc = 3.00 to 5.25 v, vss = 0 v, ta = ?0 to 85?, unless otherwise noted) symbol parameter unit limits i oh(peak) i oh(peak) i ol(peak) i ol(peak) i ol(peak) i oh(avg) i oh(avg) i ol(avg) i ol(avg) i ol(avg) i oh(peak) i oh(peak) i ol(peak) i ol(peak) i ol(peak) i oh(avg) i oh(avg) i ol(avg) i ol(avg) i ol(avg) f(x in ) f(x in ) or f(syn) f( ) ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma mhz mhz mhz mhz mhz mhz ?0 ?0 80 80 80 ?0 ?0 40 40 40 ?0 ?0 10 20 10 ? ? 5 10 5 12 6 12 6 8 6 max. ??total peak output current ( note 1 )p0 0 ?0 7 , p2 4 ?2 7 , p5 0 ?5 7 , p6 0 ?6 3 ??total peak output current ( note 1 )p1 0 ?1 7 , p3 0 ?3 7 , p4 0 ?4 3 ??total peak output current ( note 1 )p0 0 ?0 7 , p2 4 ?2 7 , p5 0 ?5 7 ??total peak output current ( note 1 )p6 0 ?6 3 ??total peak output current ( note 1 )p1 0 ?1 7 , p3 0 ?3 7 , p4 0 ?4 3 ??total average output current ( note 1 )p0 0 ?0 7 , p2 4 ?2 7 , p5 0 ?5 7 , p6 0 ?6 3 ??total average output current ( note 1 )p1 0 ?1 7 , p3 0 ?3 7 , p4 0 ?4 3 ??total average output current ( note 1 )p0 0 ?0 7 , p2 4 ?2 7 , p5 0 ?5 7 ??total average output current ( note 1 )p6 0 ?6 3 ??total average output current ( note 1 )p1 0 ?1 7 , p3 0 ?3 7 , p4 0 ?4 3 ??peak output current ( note 2 )p0 0 ?0 7 , p2 4 ?2 7 , p5 0 ?5 7 , p6 0 ?6 3 ??peak output current ( note 2 )p1 0 ?1 7 , p3 0 ?3 7 , p4 0 ?4 3 ??peak output current ( note 2 )p0 0 ?0 7 , p2 4 ?2 7 , p5 0 ?5 7 ??peak output current ( note 2 )p6 0 ?6 3 ??peak output current ( note 2 )p1 0 ?1 7 , p3 0 ?3 7 , p4 0 ?4 3 ??average output current ( note 3 )p0 0 ?0 7 , p2 4 ?2 7 , p5 0 ?5 7 , p6 0 ?6 3 ??average output current ( note 3 )p1 0 ?1 7 , p3 0 ?3 7 , p4 0 ?4 3 ??average output current ( note 3 )p0 0 ?0 7 , p2 4 ?2 7 , p5 0 ?5 7 ??average output current ( note 3 )p6 0 ?6 3 ??average output current ( note 3 )p1 0 ?1 7 , p3 0 ?3 7 , p4 0 ?4 3 main clock input oscillation frequency vcc = 4.00 to 5.25 v ( note 4 ) vcc = 3.00 to 4.00 v system clock frequency vcc = 4.00 to 5.25 v vcc = 3.00 to 4.00 v frequency vcc = 4.00 to 5.25 v vcc = 3.00 to 4.00 v typ. min. 6 6 6 6 notes 1: the total peak output current is the absolute value of the peak currents flowing through all the applicable ports. the total a verage output current is the average value of the absolute value of the currents measured over 100 ms flowing through all the applicable ports. 2: the peak output current is the absolute value of the peak current flowing in each port. 3: the average output current is the average value of the absolute value of the currents measured over 100 ms. 4: the duty of oscillation frequency is 50 %.
131 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers ??output voltage p0 0 ?0 7 , p2 4 ?2 7 , p5 0 ?5 7 , p6 0 ?6 3 ??output voltage p1 0 ?1 7 , p3 0 ?3 7 , p4 0 ?4 3 limits v v v v parameter typ. max. symbol unit test conditions table 19 electrical characteristics (1) (vcc = 3.00 to 5.25 v, vss = 0 v, ta = ?0 to 85?, unless otherwise noted) electrical characteristics i oh = ?0 ma (vcc = 4.00 to 5.25 v) i oh = ? ma i oh = ?0 ma (v cc e = 4.00 to 5.25 v) i oh = ? ma d+ and d- pins pull- down with 0 v via a resistor of 15 k ? 5 % i ol = 10 ma (vcc = 4.00 to 5.25 v) i ol = 1 ma i ol = 20 ma (vcc = 4.00 to 5.25 v) i ol = 1 ma i ol = 10 ma (v cc e = 4.00 to 5.25 v) i ol = 1 ma (v cc e = 3.00 to 5.25 v) d+ and d- pins pull-up with 3.6 v via a resistor of 1.5 k ? 5 % v i = v cc (pull-ups ?ff? v i = v cc e v i = v cc v i = v cc v i = v ss (pull-ups ?ff? v i = v ss v i = v ss v i = v ss v i = v ss (vcc = 4.00 to 5.25 v) v i = v ss when clock is stopped 2.8 0.6 0.6 0.5 3.6 2.0 1.0 2.0 1.0 2.0 1.0 0.3 5.0 5.0 5.0 ?.0 ?.0 ?.0 ?20.0 5.25 v v v v v v v v v v v ol ??output voltage d0+, d0-, d1+, d1-, d2+, d2- ??output voltage p0 0 ?0 7 , p2 4 ?2 7 , p5 0 ?5 7 ??output voltage p6 0 ?6 3 ??output voltage p1 0 ?1 7 , p3 0 ?3 7 , p4 0 ?4 3 ??output voltage d0+, d0-, d1+, d1-, d2+, d2- hysteresis cntr 0 , int 0 , int 1 hysteresis p1 0 /dq 0 ?1 7 /dq 7 , p3 0 ?3 2 , p3 3 /exint, p3 4 /excs, p3 5 /exwr, p3 6 /exrd, p3 7 / exa0, p4 0 /exdreq/rxd, p4 1 /exdack/ txd, p4 2 /extc/s clk , p4 3 /exa1/s rdy hysteresis d0+, d0-, d1+, d1-, d2+, d2- hysteresis reset ??input current p0 0 ?0 7 , p2 4 ?2 7 , p5 0 ?5 7 , p6 0 ?6 3 ??input current p1 0 ?1 7 , p3 0 ?3 7 , p4 0 ?4 3 ??input current reset, cnv ss ??input current x in ??input current p0 0 ?0 7 , p2 4 ?2 7 , p5 0 ?5 7 , p6 0 ?6 3 ??input current p1 0 ?1 7 , p3 0 ?3 7 , p4 0 ?4 3 ??input current reset, cnv ss , cnv ss2 ??input current x in ??input current p0 0 ?0 7, p5 0 , p5 2 (pull-ups ?n? ram hold voltage v t+ ? t- v t+ ? t- v ol v ol v ol 0 v t+ ? t v t+ ? t- i ih i ih i ih i ih i il i il i il i il i il v ram v v a a a a a a a a a a v 4.0 ?.0 ?0.0 ?0.0 ?0.0 2.00 v oh v oh v oh min. v cc ?.0 v cc ?.0 v cc e?.0 v cc e?.0 0.25
132 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers power source current (output transistor is isolated.) limits parameter min. typ. 23.5 24.5 24.0 22.0 13.0 6.0 2.0 125.0 0.1 max. 60 60 60 60 35 30 250 10 symbol unit test conditions i cc ma ma ma ma ma ma ma ma a a a table 20 electrical characteristics (2) (vcc = 3.00 to 5.25 v, vss = 0 v, ta = ?0 to 85?, unless otherwise noted) f(x in ) = system clock = 12 mhz, = 6 mhz, usb reference voltage circuit enabled f(x in ) = 12 mhz, system clock = = 8 mhz, usb reference voltage circuit enabled f(x in ) = 6 mhz, system clock = = 8 mhz, usb reference voltage circuit enabled f(x in ) = system clock = = 6 mhz, usb reference voltage circuit enabled f(x in ) = system clock = = 6 mhz, usb reference voltage circuit disabled f(x in ) = system clock = = 6 mhz, usb reference voltage circuit disabled f(x in ) = 12 mhz, system clock = = 8 mhz, usb reference voltage circuit enabled f(x in ) = system clock = = 6 mhz, usb reference voltage circuit disabled usb reference voltage circuit enabled low current mode usb reference voltage circuit disabled ta = 25 ? usb reference voltage circuit disabled ta = 85 ? notes 1: operating in single-chip mode clock input from x in pin (x out oscillator stopped) f usb = 48 mhz all usb difference-input circuits enabled leaving i/o pins open operating functions: pll circuit, cpu, timers 2: operating in single-chip mode with wait mode clock input from x in pin (x out oscillator stopped) f usb = 48 mhz all usb difference-input circuits enabled leaving i/o pins open operating functions: pll circuit, timers, usb receiving disabled functions: cpu 3: operating in single-chip mode with stop mode oscillation stopped all usb difference-input circuits disabled leaving i/o pins open normal mode ( note 1 ) wait mode ( note 2 ) stop mode ( note 3 ) vcc = 3.00 to 4.00 v vcc = 4.00 to 5.25 v vcc = 3.00 to 3.60 v vcc = 4.00 to 5.25 v vcc = 3.00 to 4.00 v vcc = 4.00 to 5.25 v vcc = 3.00 to 5.25 v
133 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers resolution linearity error differential nonlinear error zero transition voltage full scale transition voltage conversion time ladder resistor reference power source input current a-d port input current min. typ. max. symbol parameter limits unit test conditions ta = 25 ? ta = 25 ? 01535 lsb lsb bits ?.5 ? 10 mv 5105 50 5125 5150 mv v ot v fst t conv r ladder i vref i i(ad) a-d converter operating; v ref = 5.0 v 122 200 5 35 150 tc(x in ) or tc(f syn ) k ? 5.0 ? ? v cc = v ref = 5.12 v v cc = v ref = 5.12 v table 21 a-d converter characteristics (v cc = 3.00 to 5.25 v, v ss = 0 v, ta = ?0 to 85?, unless otherwise noted) a-d converter not operating; v ref = 5.0 v
134 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers timing requirements table 22 timing requirements (1) (v cc = 4.00 to 5.25 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit ? ns ns ns ns ns ns ns ns ns ns ns ns ns t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr) t wh (cntr) t wl (cntr) t wh (int) t wl (int) t c (s clk ) t wh (s clk ) t wl (s clk ) t su (rxd? clk ) t h (s clk ?xd) reset input ??pulse width main clock input cycle time main clock input ??pulse width main clock input ??pulse width cntr 0 input cycle time cntr 0 input ??pulse width cntr 0 input ??pulse width int 0 , int 1 input ??pulse width int 0 , int 1 input ??pulse width serial i/o clock input cycle time ( note ) serial i/o clock input ??pulse width ( note ) serial i/o clock input ??pulse width ( note ) serial i/o input set up time serial i/o input hold time 2 83 35 35 200 80 80 80 80 800 370 370 220 100 note : these limits are the rating values in the clock synchronous mode, bit 6 of address 0fe0 16 = ?? in the uart mode, bit 6 of address 0fe0 16 = ?? the rating values are set to one fourth. min. typ. max. symbol parameter limits unit ? ns ns ns ns ns ns ns ns ns ns ns ns ns t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr) t wh (cntr) t wl (cntr) t wh (int) t wl (int) t c (s clk ) t wh (s clk ) t wl (s clk ) t su (rxd? clk ) t h (s clk ?xd) reset input ??pulse width main clock input cycle time main clock input ??pulse width main clock input ??pulse width cntr 0 input cycle time cntr 0 input ??pulse width cntr 0 input ??pulse width int 0 , int 1 input ??pulse width int 0 , int 1 input ??pulse width serial i/o clock input cycle time ( note ) serial i/o clock input ??pulse width ( note ) serial i/o clock input ??pulse width ( note ) serial i/o input set up time serial i/o input hold time 2 166 70 70 500 230 230 230 230 2000 950 950 400 200 note : these limits are the rating values in the clock synchronous mode, bit 6 of address 0fe0 16 = ?? in the uart mode, bit 6 of address 0fe0 16 = ?? the rating values are set to one fourth. table 23 timing requirements (2) (v cc = 3.00 to 4.00 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted)
135 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers switching characteristics table 24 switching characteristics (1) (v cc = 4.00 to 5.25 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit t wh (s clk ) t wl (s clk ) t d (s clk ?xd) t v (s clk ?xd) t r (s clk ) t f (s clk ) t r (cmos) t f (cmos) serial i/o clock output ??pulse width serial i/o clock output ??pulse width serial i/o output delay time serial i/o output valid time serial i/o clock output rising time serial i/o clock output falling time cmos output rising time ( note ) cmos output falling time ( note ) ?0 notes: pins x out , d0+, d0-, d1+, d2-, d2+, d2- are excluded. t c (s clk )/2?0 t c (s clk )/2?0 ns ns ns ns ns ns ns ns 140 30 30 30 30 min. typ. max. symbol parameter limits unit t wh (s clk ) t wl (s clk ) t d (s clk ?xd) t v (s clk ?xd) t r (s clk ) t f (s clk ) t r (cmos) t f (cmos) serial i/o clock output ??pulse width serial i/o clock output ??pulse width serial i/o output delay time serial i/o output valid time serial i/o clock output rising time serial i/o clock output falling time cmos output rising time ( note ) cmos output falling time ( note ) ?0 notes: pins x out , d0+, d0-, d1+, d2-, d2+, d2- are excluded. t c (s clk )/2?0 t c (s clk )/2?0 ns ns ns ns ns ns ns ns 350 50 50 50 50 table 25 switching characteristics (2) (v cc = 3.00 to 4.00 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) fig. 167 output switching characteristics measurement circuit 100 pf m e a s u r e d o u t p u t p i n c m o s o u t p u t
136 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers table 26 switching characteristics (usb ports) (v cc = 3.00 to 5.25 v, v ss = 0 v, ta = 20 to 85 c, unless otherwise noted) min. typ. max. symbol parameter limits unit t fr ( d+/d- ) t ff ( d+/d- ) t lr ( d+/d- ) usb full-speed output rising time cl = 50 pf usb full-speed output rising time cl = 50 pf usb low-speed output rising time cl = 200 to 600 pf ta = 0 to 85 c cl = 250 to 600 pf ta = 20 to 85 c cl = 200 to 600 pf ta = 20 to 85 c usb low-speed output falling time cl = 200 to 600 pf ta = 0 to 85 c cl = 250 to 600 pf ta = 20 to 85 c cl = 200 to 600 pf ta = 20 to 85 c usb full-speed ports rising/falling ratio t fr ( d+/d- )/t ff ( d+/d- ) usb low-speed ports rising/falling ratio t lr ( d+/d- )/t ff ( d+/d- ) usb output signal cross-over voltage 4 4 75 75 65 75 75 65 90 80 1.3 ns ns ns ns ns ns ns ns % % v t lf ( d+/d- ) t frfm ( d+/d- ) t lrfm ( d+/d- ) vcrs( d+/d- ) 20 20 300 300 300 300 300 300 111.11 125 2.0 fig. 168 usb output switching characteristics measurement circuit (1) for d0-, d1+/d2+ (low-speed), d1-/d2- (full-speed) fig. 169 usb output switching characteristics measurement circuit (2) for d0+, d1+/d2+ (full-speed), d1-/d2- (low-speed) r l = 2 7 ? c l measured output pin r l = 1 5 k ? usb port output c l t r o n m e a s u r e d o u t p u t p i n r l = 27 ? r l = 1.5 k ? r l = 1 5 k ? u s b p o r t o u t p u t
137 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 170 timing chart 0 . 2 v c c e t d (s clk -txd) t f 0.2v cc e 0.8v cc e 0 . 8 v c c e t r t su (rxd-s clk )t h (s clk -rxd) t v ( s c l k - t x d ) t c (s clk ) t w l ( s c l k ) t wh (s clk ) r x d ( a t r e c e i v e ) s c l k 0.2v cc t wl (x in ) 0 . 8 v c c t wh (x in ) t c (x in ) x in 0 . 2 v c c 0.8v cc t w ( r e s e t ) r e s e t 0.2v cc t w l ( c n t r ) 0 . 8 v c c t w h ( c n t r ) t c ( c n t r ) 0.2v cc t w l ( i n t ) 0 . 8 v c c t w h ( i n t ) txd (at transmit) i n t 0 / i n t 1 c n t r 0
138 38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers lqfp64-p-1414-0.8 weight(g) jedec code eiaj package code lead material cu alloy 64p6u-a plastic 64pin 14 14mm body lqfp 0.1 0.8 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.225 i 2 m d 14.4 m e 14.4 0 ? 8 ? 0.1 0.2 1.0 0.7 0.5 0.3 16.2 15.8 14.1 13.9 16.2 15.8 14.0 14.1 13.9 14.0 16.0 16.0 0.175 0.125 0.105 0.45 0.37 0.32 1.4 0 1.7 e under planning lp 0.45 0.95 0.6 0.25 0.75 x a3 recommended mount pad detail f mmp e h e 1 17 32 64 49 16 48 33 h d d a y b x m e f m d l 2 b 2 m e e a 1 a 2 l 1 l lp a3 c package outline
38k2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers ?2002 mitsubishi electric corp. new publication, effective march 2002. specifications subject to change without notice. notes regarding these materials these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product b est suited to the customer? application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party? rights, origina ting in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents inf ormation on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that c ustomers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assu mes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubish i semiconductor home page (http://www.mitsubishichips.com). when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used und er circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herei n for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these m aterials. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a licen se from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further detai ls on these materials or the products contained therein. keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with a ppropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. head office: 2-2-3, marunouchi, chiyoda-ku, tokyo 100-8310, japan lqfp64-p-1010-0.50 weight(g) jedec code eiaj package code lead material cu alloy 64p6q-a plastic 64pin 10 ? 10mm body lqfp 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.225 i 2 1.0 m d 10.4 m e 10.4 10 0 0.1 1.0 0.7 0.5 0.3 12.2 12.0 11.8 12.2 12.0 11.8 0.5 10.1 10.0 9.9 10.1 10.0 9.9 0.175 0.125 0.105 0.28 0.18 0.13 1.4 0 1.7 e e e h e 1 64 49 48 33 32 17 16 h d d m d m e a f y b 2 i 2 recommended mount pad lp 0.45 0.6 0.25 0.75 0.08 x a3 b x m a 1 a 2 l 1 l detail f lp a3 c e mmp
revision history 38k2 group data sheet rev. date description page summary (1/2) 1.0 7/6/01 1.1 7/19/01 first edition issued fig.24: vrefcon.....1: low current mode p4 1 /exdack/txd pin p4 2 /extc/s clk pin fig.102: int_ctr.....0 0 1: rxb_rdy some features are revised: power source voltage, power dissipation, operating temperature range. fig.1: the design of top view is revised. table 1: the function of vcc, vcce and usbv ref is revised. 100d0m package is added. table 2: the product m38k29rfs is added. fig. 7: the description of system clock division ratio selection bits is revised. the explanations from pages 25 to 30 are added. fig. 29: in (6) endpoint 11 bit name of ep11req is revised. fig. 31: the function is revised. fig. 70: the function is revised. the explanations from pages 57 to 60 are added. fig. 106: bit name of exbireq. is revised: fig. 108: note is added. fig. 109: bit attributes are revised. fig. 114: register symbol is revised. the explanations of a-d converter are revised. the voltages regarding reset is revised. the clock frequency regarding pll is revised. fig. 144 is added. the explanations of flash memory mode and table 9 are revised. the explanations of microcomputer mode and boot mode, and fig.145 are revised. the explanations of operation speed are revised. the explanations of (2) parallel i/o mode are revised. the explanations of (3) standard serial i/o mode are revised. table 12: the function of vcce, cnvss, p1 0 to p1 5 , p1 6 and p1 7 is revised. fig. 153: the descriptions of ce and s clk are added. fig. 165: p1 6 (ce) is added. the explanations of instruction execution time are revised. the explanations of definition of a-d conversion accuracy is added. p. 26 p. 64 p. 68 p. 1 2.0 2/14/02 p. 3 p. 5 p. 9 p. 25?0 p. 31 p. 32 p. 50 p. 57?0 p. 75 p. 76 p. 78 p. 90 p. 93 p. 94 p. 98 p. 99 p. 100 p. 103 p. 110 p. 111 p. 112 p. 113 p. 124 p. 125 p. 126
revision history 38k2 group data sheet rev. date description page summary (2/2) the explanations are added: usb port pins, usbv ref pin treatment and electric characteristic differences between mask rom and flash memory version mcus. table 16: operating temperature is revised. table 17: measuring conditions, power source voltage vcc and analog power source voltage vcce are revised. analog power source voltage usbv ref is added. table 18: measuring conditions, f(x in ) and notes 1 and 2 are revised. [f(x in ) or f(syn)] and f( ) are added. table 19: measuring conditions and some of v oh , v ol , v t +? t - and i il are re- vised or added. table 20: the information are revised. table 21: measuring conditions and i vref are revised. tables 22 to 26: the information are revised or added. figures 168 and 169 are added. the symbol ?reliminary?is deleted from the header. some explanations of pll circuit are deleted. table 12: vcc apply voltage is revised. fig. 170: the symbols in s clk and rxd are revised. 2.0 2/14/02 p. 127 p. 128 p. 129 p. 130 p. 131 p. 132 p. 133 p. 134 to 136 p. 136 all pages p. 94 p. 112 p. 137 2.1 2/18/02 2.2 3/05/02

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